The ID_ISAR2 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See.
ID_ISAR2 is architecturally mapped to AArch64 register ID_ISAR2_EL1. See AArch32 Instruction Set Attribute Register 2.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_ISAR2 is a 32-bit register.
Figure 4.88 shows the ID_ISAR2 bit assignments.
Table 4.179 shows the ID_ISAR2 bit assignments.
Indicates the implemented Reversal instructions:
Indicates the implemented A and R profile instructions to manipulate the PSR:
The exception return forms of the data-processing instructions are:
Indicates the implemented advanced unsigned Multiply instructions:
Indicates the implemented advanced signed Multiply instructions.
Indicates the implemented additional Multiply instructions:
Indicates the support for interruptible multi-access instructions:
Indicates the implemented memory hint instructions:
Indicates the implemented additional load/store instructions:
To access the ID_ISAR2:
MRC p15, 0, <Rt>, c0, c2, 2 ; Read ID_ISAR2 into Rt
Register access is encoded as follows: