The MIDR characteristics are:
Provides identification information for the processor, including an implementer code for the device and a device ID number.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
The MIDR is:
Architecturally mapped to the AArch64 MIDR_EL1 register. See Multiprocessor Affinity Register.
Architecturally mapped to external MIDR_EL1 register.
MIDR is a 32-bit register.
Figure 4.76 shows the MIDR bit assignments.
Table 4.155 shows the MIDR bit assignments.
Indicates the implementer code. This value is:
Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status. This value is:
Indicates the architecture code. This value is:
Indicates the primary part number. This value is:
Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is:
To access the MIDR:
MRC p15, 0, <Rt>, c0, c0, 0; Read MIDR into Rt
Register access is encoded as follows:
The MIDR can be accessed through the internal memory-mapped
interface and the external debug interface, offset