The MAIR0 and MAIR1 characteristics are:
To provide the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
- Usage constraints
These registers are accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
AttrIndx, from the translation table descriptor, selects the appropriate MAIR: setting AttrIndx to 0 selects MAIR0.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
The Secure copy of the register gives the value for memory accesses from Secure state.
The Non-secure copy of the register gives the value for memory accesses from Non-secure states other than Hyp mode.
MAIR0 (NS) is architecturally mapped to AArch64 register MAIR_EL1[31:0] when TTBCR.EAE==1. See Memory Attribute Indirection Register, EL1.
MAIR0 (S) is mapped to AArch64 register MAIR_EL3[31:0] when TTBCR.EAE==1. See Memory Attribute Indirection Register, EL3.
There are separate Secure and Non-secure copies of this register.
MAIR0 has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH.
MAIR0 is a 32-bit register when TTBCR.EAE==1.
Figure 4.134 shows the MAIR0 and MAIR1 bit assignments.
Table 4.240 shows the MAIR0 and MAIR1 bit assignments.
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
[a] Where m is 0-7.
Table 4.241 shows the Attr<n>[7:4] bit assignments.
|Device memory. See Table 4.242 for the type of Device memory.|
|Normal Memory, Outer Write-through transient.[a]|
|Normal Memory, Outer Non-Cacheable.|
|Normal Memory, Outer Write-back transient.[a]|
|Normal Memory, Outer Write-through non-transient.|
|Normal Memory, Outer Write-back non-transient.|
[a] The transient hint is ignored.
|Bits||Meaning when Attr<n>[7:4] is 0000||Meaning when Attr<n>[7:4] is not 0000|
|unpredictable||Normal Memory, Inner Write-through transient|
|Device-nGnRE memory||Normal memory, Inner Non-Cacheable|
|unpredictable||Normal Memory, Inner Write-back transient|
|Device-nGRE memory||Normal Memory, Inner Write-throughnon-transient (RW=00)|
|unpredictable||Normal Memory, Inner Write-through non-transient|
|Device-GRE memory||Normal Memory, Inner Write-back non-transient (RW=00)|
|unpredictable||Normal Memory, Inner Write-back non-transient|
To access the MAIR0:
MRC p15, 0, <Rt>, c10, c2, 0 ; Read MAIR0 into Rt MCR p15, 0, <Rt>, c10, c2, 0 ; Write Rt to MAIR0
To access the MAIR1:
MRC p15, 0, <Rt>, c10, c2, 1 ; Read MAIR1 into Rt MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to MAIR1