The SCR characteristics are:
Defines the configuration of the current security state. It specifies:
The security state of the processor, Secure or Non-secure.
What state the processor branches to, if an IRQ, FIQ or external abort occurs.
Whether the CPSR.F and CPSR.A bits can be modified when SCR.NS = 1.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW - RW RW
Any read or write to SCR in Secure EL1 state in AArch32 is trapped as an exception to EL3.
The SCR is a Restricted access register that exists only in the Secure state.
The SCR is mapped to the AArch64 SCR_EL3 register.
SCR is a 32-bit register.
Figure 4.101 shows the SCR bit assignments.
Table 4.203 shows the SCR bit assignments.
Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:
Hyp Call enable. This bit enables use of the HVC instruction from Non-secure EL1 modes. The possible values are:
Secure Monitor Call disable. Makes the SMC instruction undefined in Non-secure state. The possible values are:
A trap of the SMC instruction to Hyp mode takes priority over the value of this bit.
Not Early Termination. This bit disables early termination.
This bit is not implemented, res0.
A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state.
F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state:
External Abort handler. This bit controls which mode takes external aborts. The possible values are:
FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the processor. The possible values are:
To access the SCR:
MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR