The SCTLR characteristics are:
Provides the top level control of the system, including its memory system.
- Usage constraints
The SCTLR is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value that most closely reflects that implementation, and ignore writes.
Some bits in the register are read-only. These bits relate to non-configurable features of an implementation, and are provided for compatibility with previous versions of the architecture.
SCTLR (NS) is architecturally mapped to AArch64 register SCTLR_EL1. See System Control Register, EL1.
If EL3 is using AArch32, there are separate Secure and Non-secure copies of this register.
SCTLR has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH.
SCTLR is a 32-bit register.
Figure 4.98 shows the SCTLR bit assignments.
Table 4.200 shows the SCTLR bit assignments.
T32 Exception enable. This bit controls whether exceptions are taken in A32 or T32 state:
The input CFGTE defines the reset value of the TE bit.
Access Flag Enable. This bit enables use of the AP bit in the translation descriptors as the Access flag. It also restricts access permissions in the translation descriptors to the simplified model:
TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme used to describe the memory region attributes in the VMSA:
Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups:
The input CFGEND defines the reset value of the EE bit.
Unprivileged write permission implies EL1 Execute Never (XN). This bit can be used to require all memory regions with unprivileged write permissions to be treated as XN for accesses from software executing at EL1.
Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN.
Not trap WFE.
Not trap WFI.
Vectors bit. This bit selects the base address of the exception vectors:
The input VINITHI defines the reset value of the V bit.
Instruction cache enable bit. This is a global enable bit for instruction caches:
CP15 barrier enable.
Cache enable. This is a global enable bit for data and unified caches:
Alignment check enable. This is the enable bit for Alignment fault checking:
MMU enable. This is a global enable bit for the MMU stage 1 address translation:
To access the SCTLR:
MRC p15, 0, <Rt>, c1, c0, 0 ; Read SCTLR into Rt MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR