The VTCR characteristics are:
Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure modes other than Hyp mode, and holds cacheability and shareability information for the accesses.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW -
Used in conjunction with VTTBR, that defines the translation table base address for the translations.
VTCR is architecturally mapped to AArch64 register VTCR_EL2. See Virtualization Translation Control Register, EL2.
This register is accessible only at EL2 or EL3.
VTCR is a 32-bit register.
Figure 4.118 shows the VTCR bit assignments.
Table 4.220 shows the VTCR bit assignments.
Shareability attribute for memory associated with translation table walks using TTBR0.
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
Starting level for translation table walks using VTTBR:
|||S||Sign extension bit. This bit must be programmed to the value of T0SZ. If it is not, then the stage 2 T0SZ value is treated as an unknown value within the legal range that can be programmed.|
The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.
To access the VTCR:
MRC p15, 4, <Rt>, c2, c1, 2; Read VTCR into Rt MCR p15, 4, <Rt>, c2, c1, 2; Write Rt to VTCR