You copied the Doc URL to your clipboard.

4.4.20. AArch32 Virtual memory control registers

Table 4.145 shows the virtual memory control registers.

Table 4.145. Virtual memory control registers
NameCRnOp1CRmOp2ResetWidthDescription
SCTLRc10c000x00C50838[a]32-bit

System Control Register

TTBR0c20c00UNK32-bitTranslation Table Base Register 0, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
-0c2-64-bit
TTBR1 0c01UNK32-bitTranslation Table Base Register 1, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
-1c2-64-bit
TTBCR 0c02

0x00000000[b]

32-bit

Translation Table Base Control Register

DACRc30c00UNK32-bitDomain Access Control Register
PRRRc100c20UNK32-bitPrimary Region Remap Register
MAIR0 0UNK32-bit

Memory Attribute Indirection Registers 0 and 1

NMRR 1UNK32-bit

Normal Memory Remap Register

MAIR1 1UNK32-bitMemory Attribute Indirection Registers 0 and 1
AMAIR0c300x0000000032-bitAuxiliary Memory Attribute Indirection Register 0
AMAIR110x0000000032-bitAuxiliary Memory Attribute Indirection Register 1
CONTEXTIDRc130c01UNK32-bit

Process ID Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

[a] The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.145 assumes these signals are set to LOW.

[b] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


Was this page helpful? Yes No