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4.4.16. c14 registers

Table 4.141 shows the CP15 system registers when the processor is in AArch32 state and the value of CRn is c14. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.141. c14 register summary

Timer Counter Frequency Register


Timer Control Register


Physical Timer TimerValue Register



Physical Timer Control Register


Virtual Timer TimerValue Register


Counter-timer Virtual Timer Control Register

 c80PMEVCNTR0UNKPerformance Monitor Event Count Registers

Performance Monitor Event Type Registers

 c157PMCCFILTR0x00000000Performance Monitor Cycle Count Filter Register.


Timer Control Register (EL2)
 c20CNTHP_TVALUNKPhysical Timer TimerValue (EL2)
  1CNTHP_CTL-[b]Physical Timer Control Register (EL2)

[a] The reset value for bits[9:8, 2:0] is 0b00000.

[b] The reset value for bit[0] is 0.

[c] The reset value for bit[2] is 0 and for bits[1:0] is 0b11.