The ID_DFR0_EL1 characteristics are:
Provides top level information about the debug system in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_DFR0_EL1 is architecturally mapped to AArch32 register ID_DFR0. See Debug Feature Register 0.
ID_DFR0_EL1 is a 32-bit register.
Figure 4.6 shows the ID_DFR0_EL1 bit assignments.
Table 4.28 shows the ID_DFR0_EL1 bit assignments.
Indicates support for performance monitor model:
Indicates support for memory-mapped debug model for M profile processors:
Indicates support for memory-mapped trace model:
In the Trace registers, the ETMIDR gives more information about the implementation.
Indicates support for coprocessor-based trace model:
Indicates support for coprocessor-based Secure debug model:
Indicates support for coprocessor-based debug model:
To access the ID_DFR0_EL1:
MRS <Xt>, ID_DFR0_EL1 ; Read ID_DFR0_EL1 into Xt
Register access is encoded as follows: