The ID_ISAR3_EL1 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_ISAR3_EL1 is architecturally mapped to AArch32 register ID_ISAR3. See Instruction Set Attribute Register 3.
ID_ISAR3_EL1 is a 32-bit register.
Figure 4.14 shows the ID_ISAR3_EL1 bit assignments.
Table 4.44 shows the ID_ISAR3_EL1 bit assignments.
Indicates the implemented Thumb Execution Environment (T32EE) instructions:
Indicates support for True NOP instructions:
Indicates the support for T32 non flag-setting
Indicates the implemented Table Branch instructions in the T32 instruction set.
Indicates the implemented Synchronization Primitive instructions:
Indicates the implemented SVC instructions:
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
Indicates the implemented Saturate instructions:
To access the ID_ISAR3_EL1:
MRS <Xt>, ID_ISAR3_EL1 ; Read ID_ISAR3_EL1 into Xt
Register access is encoded as follows: