The CPTR_EL3 characteristics are:
Controls trapping to EL3 for accesses to CPACR, Trace functionality and registers associated with Advanced SIMD and Floating-point execution. Controls EL3 access to this functionality.
CPTR_EL3 is part of the Security registers functional group.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW
There are no configuration notes.
CPTR_EL3 is a 32-bit register.
Figure 4.42 shows the CPTR_EL3 bit assignments.
Table 4.86 shows the CPTR_EL3 bit assignments.
This causes a direct access to the CPACR_EL1 from EL1 or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. The possible values are:
Trap Trace Access.
Not implemented. res0.
This causes instructions that access the registers associated with Advanced SIMD or floating-point execution to trap to EL3 when executed from any exception level, unless trapped to EL1 or EL2. The possible values are:
To access the CPTR_EL3:
MRS <Xt>, CPTR_EL3 ; Read CPTR_EL3 into Xt MSR CPTR_EL3, <Xt> ; Write Xt to CPTR_EL3