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4.3.59. Exception Syndrome Register, EL2

The ESR_EL2 characteristics are:

Purpose

Holds syndrome information for an exception taken to EL2.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RWRWRW
Configurations

ESR_EL2 is architecturally mapped to AArch32 register HSR. See Hyp Syndrome Register.

Attributes

ESR_EL2 is a 32-bit register.

Figure 4.53 shows the ESR_EL2 bit assignments.

Figure 4.53. ESR_EL2 bit assignments

Figure 4.53. ESR_EL2 bit assignments

Table 4.99 shows the ESR_EL2 bit assignments.

Table 4.99.  ESR_EL2 bit assignments
BitsNameFunction
[31:26]ECException Class. Indicates the reason for the exception that this register holds information about.
[25]IL

Instruction Length for synchronous exceptions. The possible values are:

0

16-bit.

1

32-bit.

[24:0]ISS

Syndrome information.


To access the ESR_EL2:

MRS <Xt>, ESR_EL2 ; Read EL1 Exception Syndrome Register
MSR ESR_EL2, <Xt> ; Write EL1 Exception Syndrome Register
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