The FAR_EL2 characteristics are:
Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions from a misaligned PC or a Watchpoint debug event, taken to EL2.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW RW RW
FAR_EL2[31:0] is architecturally mapped to AArch32 registers:
FAR_EL2[63:32] is architecturally mapped to AArch32 registers:
FAR_EL2 is a 64-bit register.
Figure 4.56 shows the FAR_EL2 bit assignments.
The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from a misaligned PC, taken in EL2.
If a memory fault that sets the FAR is generated from one of the data cache instructions, this field holds the address specified in the register argument of the instruction.
To access the FAR_EL2:
MRS <Xt>, FAR_EL2 ; Read EL2 Fault Address Register MSR FAR_EL2, <Xt> ; Write EL2 Fault Address Register