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4.3.77. Interrupt Status Register

The ISR_EL1 characteristics are:

Purpose

Shows whether an IRQ, FIQ, or external abort is pending. An indicated pending abort might be a physical abort or a virtual abort.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

ISR_EL1 is architecturally mapped to AArch32 register ISR. See Interrupt Status Register.

Attributes

ISR_EL1 is a 32-bit register.

Figure 4.70 shows the ISR_EL1 bit assignments.

Figure 4.70. ISR_EL1 bit assignments

Figure 4.70. ISR_EL1 bit assignments

Table 4.119 shows the ISR_EL1 bit assignments.

Table 4.119. ISR_EL1 bit assignments
BitsNameFunction
[31:9]-

Reserved, res0.

[8]A

External abort pending bit:

0

No pending external abort.

1

An external abort is pending.

[7]I

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

0

No pending IRQ.

1

An IRQ interrupt is pending.

[6]F

FIQ pending bit. Indicates whether an FIQ interrupt is pending:

0

No pending FIQ.

1

An FIQ interrupt is pending.

[5:0]-

Reserved, res0.


To access the ISR_EL1:

MRS <Xt>, ISR_EL1 ; Read ISR_EL1 into Xt

Register access is encoded as follows:

Table 4.120. ISR_EL1 access encoding
op0op1CRnCRmop2
1100011000001000

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