The L2ACTLR_EL1 characteristics are:
Provides configuration and control options for the L2 memory system.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
This register can be written only when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.
If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:
Disable the MMU from each core followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.
Ensure that the system has no outstanding AC channel coherence requests to the Cortex-A53 processor.
Ensure that the system has no outstanding ACP requests to the Cortex-A53 processor.
When the L2 memory system is idle, the processor can update the L2ACTLR_EL1 followed by an
ISB. After the L2ACTLR_EL1 is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.
There is one copy of this register that is used in both Secure and Non-secure states.
L2ACTLR_EL1 is mapped to the AArch32 L2ACTLR register. See L2 Auxiliary Control Register.
L2ACTLR_EL1 is a 32-bit register.
Figure 4.60 shows the L2ACTLR_EL1 bit assignments.
Table 4.106 shows the L2ACTLR_EL1 bit assignments.
L2 Victim Control.
|||Enable UniqueClean evictions with data|
Enables sending of WriteEvict transactions for UniqueClean evictions with data.
WriteEvict transactions update downstream caches that are outside the cluster. Enable WriteEvict transactions only if there is an L3 or system cache implemented in the system.
The possible values are:
Some ACE interconnects might not support the WriteEvict transaction. You must not enable this bit if your interconnect does not support WriteEvict transactions.
|||Disable clean/evict push to external|
Disables sending of Evict transactions for clean cache lines that are evicted from the processor. This is required only if the external interconnect contains a snoop filter that requires notification when the processor evicts the cache line. The possible values are:
To access the L2ACTLR_EL1:
MRS Rt, S3_1_C15_C0_0; Read L2ACTLR_EL1 into Rt MSR S3_1_C15_C0_0, Rt; Write Rt to L2ACTLR_EL1