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Error injection

To support testing of error handling software, the Cortex-A53 processor provides the capability to force double-bit errors to be injected into the L1 D-cache data RAMs, the L2 data RAMs, and the L2 tag RAMs.

Error injection on the L1 D-cache data RAMs is enabled by setting the CPUACTLR.L1DEIEN bit. While this bit is set, double-bit errors are injected on all writes to the L1 D-cache data RAMs for the first word of each 32-byte region. This corresponds to bytes with an address where bits [4:2] are 0b000. The L1 D-cache RAMs can be written to because of:

  • Explicit stores from the core.

  • Cache line fetches into the cache, as a result of:

    • Load instructions.

    • Store instructions.

    • Preload instructions.

    • Data prefetches.

    • Pagewalks.

Error injection on the L2 data RAMs is enabled by setting the L2ACTLR.L2DEIEN bit. While this bit is set, double-bit errors are injected on all writes to the L2 cache data RAMs. The L2 data RAMs can be written to because of:

  • Explicit stores from one of the cores.

  • Instruction fetches or prefetches.

  • Evictions from the L1 Data cache.

  • ACP accesses.

Error injection on the L2 tag RAMs is enabled by setting the L2ACTLR.L2TEIEN bit. While this bit is set, double-bit errors are injected on all writes to the L2 tag RAMs. The L2 cache tag RAMs can be written because of:

  • Explicit stores from one of the cores.

  • L2 allocations caused by instruction fetches or prefetches.

  • Evictions from the L1 Data cache.

  • ACP accesses.

  • Snoop operations.

  • Cache maintenance instructions.

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