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CTI Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM CoreSight architecture. There is a set of eight registers, listed in register number order in Table 14.8.

Table 14.8. Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4 0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0xA8 0xFE0
Peripheral ID1 0xB9 0xFE4
Peripheral ID2 0x4B 0xFE8
Peripheral ID3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The Peripheral ID registers are:

Peripheral Identification Register 0

The CTIPIDR0 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTIPIDR0 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 14.4 describes the condition codes.

Configurations

CTIPIDR0 is in the Debug power domain.

CTIPIDR0 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.4 shows the CTIPIDR0 bit assignments.

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Table 14.9 shows the CTIPIDR0 bit assignments.

Table 14.9. CTIPIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] Part_0
0xA8

Least significant byte of the cross trigger part number.


CTIPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

Peripheral Identification Register 1

The CTIPIDR1 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTIPIDR1 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 14.4 describes the condition codes.

Configurations

CTIPIDR1 is in the Debug power domain.

CTIPIDR1 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.5 shows the CTIPIDR1 bit assignments.

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Table 14.10 shows the CTIPIDR1 bit assignments.

Table 14.10. CTIPIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0] Part_1
0x9

Most significant nibble of the CTI part number.


CTIPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Peripheral Identification Register 2

The CTIPIDR2 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTIPIDR2 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 14.4 describes the condition codes.

Configurations

CTIPIDR2 is in the Debug power domain.

CTIPIDR2 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.6 shows the CTIPIDR2 bit assignments.

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Table 14.11 shows the CTIPIDR2 bit assignments.

Table 14.11. CTI PIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Revision
0x4

r0p4.

[3] JEDEC
0b1

res1. Indicates a JEP106 identity code is used.

[2:0] DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


CTIPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Peripheral Identification Register 3

The CTIPIDR3 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTIPIDR3 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 14.4 describes the condition codes.

Configurations

CTIPIDR3 is in the Debug power domain.

CTIPIDR3 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.7 shows the CTIPIDR3 bit assignments.

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Table 14.12 shows the CTIPIDR3 bit assignments.

Table 14.12. CTIPIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] REVAND
0x0

Part minor revision.

[3:0] CMOD
0x0

Customer modified.


CTIPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Peripheral Identification Register 4

The CTIPIDR4 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTIPIDR4 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 14.4 describes the condition codes.

Configurations

CTIPIDR4 is in the Debug power domain.

CTIPIDR4 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.8 shows the CTIPIDR4 bit assignments.

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Table 14.13 shows the CTIPIDR4 bit assignments.

Table 14.13. CTIPIDR4 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.

[3:0] DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


CTIPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are res0.

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