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AArch32 debug register summary

Table 11.7 summarizes the 32-bit and 64-bit debug control registers that are accessible in the AArch32 Execution state from the internal CP14 interface. These registers are accessed by the MCR and MRC instructions in the order of CRn, op2, CRm, Op1 or MCRR and MRRC instructions in the order of CRm, Op1. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

See the Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped and the external debug interface.

Table 11.7. AArch32 debug register summary
Offset CRn Op2 CRm Op1 Name Type Description
- c0 0 c0 0 DBGDIDR RO Debug ID Register
- c0 0 c1 0 DBGDSCRint RO Debug Status and Control Register, Internal View
- c0 0 c2 0 DBGDCCINT RW Debug Comms Channel Interrupt Enable Register
0x08C c0 0 c5 0 DBGDTRTXint WO Debug Data Transfer Register, Transmit, Internal View
          DBGDTRRXint RO Debug Data Transfer Register, Receive, Internal View
- c0 0 c6 0 DBGWFAR[a] RW Watchpoint Fault Address Register, res0
- c0 0 c7 0 DBGVCR RW Debug Vector Catch Register
- c0 2 c0 0 DBGDTRRXext RW Debug Data Transfer Register, Receive, External View
- c0 2 c2 0 DBGDSCRext RW Debug Status and Control Register, External View
- c0 2 c3 0 DBGDTRTXext RW Debug Data Transfer Register, Transmit, External View
0x098 c0 2 c6 0 DBGOSECCR RW Debug OS Lock Exception Catch Control Register
0x400 c0 4 c0 0 DBGBVR0 RW Debug Breakpoint Value Register 0
0x410 c0 4 c1 0 DBGBVR1 RW Debug Breakpoint Value Register 1
0x420 c0 4 c2 0 DBGBVR2 RW Debug Breakpoint Value Register 2
0x430 c0 4 c3 0 DBGBVR3 RW Debug Breakpoint Value Register 3
0x440 c0 4 c4 0 DBGBVR4 RW Debug Breakpoint Value Register 4
0x450 c0 4 c5 0 DBGBVR5 RW Debug Breakpoint Value Register 5
0x408 c0 5 c0 0 DBGBCR0 RW Debug Breakpoint Control Registers, EL1
0x418 c0 5 c1 0 DBGBCR1 RW Debug Breakpoint Control Registers, EL1
0x428 c0 5 c2 0 DBGBCR2 RW Debug Breakpoint Control Registers, EL1
0x438 c0 5 c3 0 DBGBCR3 RW Debug Breakpoint Control Registers, EL1
0x448 c0 5 c4 0 DBGBCR4 RW Debug Breakpoint Control Registers, EL1
0x458 c0 5 c5 0 DBGBCR5 RW Debug Breakpoint Control Registers, EL1
0x800 c0 6 c0 0 DBGWVR0 RW Debug Watchpoint Value Register 0
0x810 c0 6 c1 0 DBGWVR1 RW Debug Watchpoint Value Register 1
0x820 c0 6 c2 0 DBGWVR2 RW Debug Watchpoint Value Register 2
0x830 c0 6 c3 0 DBGWVR3 RW Debug Watchpoint Value Register 3
0x808 c0 7 c0 0 DBGWCR0 RW Debug Watchpoint Control Registers, EL1
0x818 c0 7 c1 0 DBGWCR1 RW Debug Watchpoint Control Registers, EL1
0x828 c0 7 c2 0 DBGWCR2 RW Debug Watchpoint Control Registers, EL1
0x838 c0 7 c3 0 DBGWCR3 RW Debug Watchpoint Control Registers, EL1
- c1 0 c0 0 DBGDRAR[31:0] RO Debug ROM Address Register
- - - c1 - DBGDRAR[63:0] RO
0x444 c1 1 c4 0 DBGBXVR4 RW Debug Breakpoint Extended Value Register 4
0x454 c1 1 c5 0 DBGBXVR5 RW Debug Breakpoint Extended Value Register 5
0x300 c1 4 c0 0 DBGOSLAR WO Debug OS Lock Access Register
- c1 4 c1 0 DBGOSLSR RO Debug OS Lock Status Register
- c1 4 c3 0 DBGOSDLR RW Debug OS Double Lock Register
0x310 c1 4 c4 0 DBGPRCR RW Debug Power/Reset Control Register
- c2 2 c0 0 DBGDSAR[31:0][b] RO Debug Self Address Register res0
- - 0 c2 - DBGDSAR[63:0][b] RO
- c7 7 c0 0 DBGDEVID2 RO Debug Device ID Register 2, res0
- c7 7 c1 0 DBGDEVID1 RO Debug Device ID Register 1
- c7 7 c2 0 DBGDEVID RO Debug Device ID Register
0xFA0 c7 6 c8 0 DBGCLAIMSET RW Debug Claim Tag Set Register
0xFA4 c7 6 c9 0 DBGCLAIMCLR RW Debug Claim Tag Clear Register
0xFB8 c7 6 c14 0 DBGAUTHSTATUS RO Debug Authentication Status Register

[a] Previously returned information about the address of the instruction that accessed a watchpoint address. This register is now deprecated and is res0.

[b] Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the processor. This register is now deprecated and res0.


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