External access permission to the debug registers is subject to the conditions at the time of the access. Table 11.1 describe the processor response to accesses through the external debug interface.
|Off||EDPRSR.PU is 0||
Processor power domain is completely off, or in a low-power state where the processor power domain registers cannot be accessed.
If debug power is off then all external debug and memory-mapped register accesses return an error.
|DLK||EDPRSR.DLK is 1||OS Double Lock is locked.|
|OSLK||OSLSR_EL1.OSLK is 1||OS Lock is locked.|
||External debug access is disabled. When an error is returned because of an EDAD condition code, and this is the highest priority error condition, EDPRSR.SDAD is set to 1. Otherwise SDAD is unchanged.|
|SLK||Memory-mapped interface only||Software lock is locked. For the external debug interface, ignore this column.|
|Default||-||None of the conditions apply, normal access.|
Table 11.2 shows an example of external register condition codes for access to a performance monitor register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops.