When set HIGH, the DBGL1RSTDISABLE input signal disables the automatic hardware controlled invalidation of the L1 data cache after the processor is reset, using nCORERESET or nCPUPORESET.
The DBGL1RSTDISABLE must be used only to assist debug of an external watchdog triggered reset by allowing the contents of the L1 data cache prior to the reset to be observable after the reset. If reset is asserted, while an L1 data cache eviction or L1 data cache fetch is performed, the accuracy of those cache entries is not guaranteed.
You must not use the DBGL1RSTDISABLE signal to disable automatic hardware controlled invalidation of the L1 data cache in normal processor powerup sequences. This is because synchronisation of the L1 data cache invalidation sequence with the duplicate L1 tags in the SCU is not guaranteed.
The DBGL1RSTDISABLE signal applies to all cores in the cluster. Each core samples the signal when nCORERESET or nCPUPORESET is asserted.
If the functionality offered by the DBGL1RSTDISABLE input signal is not required, the input must be tied to LOW.