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Debug memory map

The basic memory map supports up to four cores in the cluster. Table 11.27 shows the address mapping for the Cortex-A53 processor debug APB components when configured for v8 Debug memory map.

Each component in the table requires 4KB, and uses the bottom 4KB of each 64KB region. The remaining 60KB of each region is reserved.

Table 11.27. Address mapping for APB components
Address offset [21:0] Component[a]
0x000000 - 0x000FFF Cortex-A53 APB ROM table
0x010000 - 0x010FFF CPU 0 Debug
0x020000 - 0x020FFF CPU 0 CTI
0x030000 - 0x030FFF CPU 0 PMU
0x040000 - 0x040FFF CPU 0 Trace
0x041000 - 0x10FFFF Reserved
0x110000 - 0x110FFF CPU 1 Debug
0x120000 - 0x120FFF CPU 1 CTI
0x130000 - 0x130FFF CPU 1 PMU
0x140000 - 0x140FFF CPU 1 Trace
0x141000 - 0x20FFFF Reserved
0x210000 - 0x210FFF CPU 2 Debug
0x220000 - 0x220FFF CPU 2 CTI
0x230000 - 0x230FFF CPU 2 PMU
0x240000 - 0x240FFF CPU 2 Trace
0x241000 - 0x30FFFF Reserved
0x310000 - 0x310FFF CPU 3 Debug
0x320000 - 0x320FFF CPU 3 CTI
0x330000 - 0x330FFF CPU 3 PMU
0x340000 - 0x340FFF CPU 3 Trace
0x341000 - 0x3FFFFF Reserved

[a] Indicates the mapped component if present, otherwise reserved.


Table 11.28 shows the address mapping for the Cortex-A53 processor debug APB components when configured for v7 Debug memory map.

Table 11.28. Address mapping for APB components
Address offset [21:0] Component[a]
0x00000 - 0x00FFF Cortex-A53 APB ROM table
0x01000 - 0x07FFF Reserved for other debug components
0x08000 - 0x0FFFF Reserved for future expansion
0x10000 - 0x10FFF CPU 0 Debug
0x11000 - 0x11FFF CPU 0 PMU
0x12000 - 0x12FFF CPU 1 Debug
0x13000 - 0x13FFF CPU 1 PMU
0x14000 - 0x14FFF CPU 2 Debug
0x15000 - 0x15FFF CPU 2 PMU
0x16000 - 0x16FFF CPU 3 Debug
0x17000 - 0x17FFF CPU 3 PMU
0x18000 - 0x18FFF CPU 0 CTI
0x19000 - 0x19FFF CPU 1 CTI
0x1A000 - 0x1AFFF CPU 2 CTI
0x1B000 - 0x1BFFF CPU 3 CTI
0x1C000 - 0x1CFFF CPU 0 Trace
0x1D000 - 0x1DFFF CPU 1 Trace
0x1E000 - 0x1EFFF CPU 2 Trace
0x1F000 - 0x1FFFF CPU 3 Trace

[a] Indicates the mapped component if present, otherwise reserved.


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