The EDRCR characteristics are:
This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.
This register is part of the Debug registers functional group.
- Usage constraints
This registers is accessible as follows:
Off DLK OSLK SLK Default Error Error Error WI WO
EDRCR is in the Core power domain.
See the register summary in Table 11.3.
EDRCR is a 32-bit register.
Figure 11.8 shows the EDRCR bit assignments.
Table 11.12 shows the EDRCR bit assignments.
Allow imprecise entry to Debug state. The actions on writing to this bit are:
Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:
Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:
The EDRCR can be accessed through the internal memory-mapped
interface and the external debug interface, offset