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Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface v5 specification. They are a set of eight registers, listed in register number order in Table 11.16.

Table 11.16. Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4 0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0x03 0xFE0
Peripheral ID1 0xBD 0xFE4
Peripheral ID2 0x4B 0xFE8
Peripheral ID3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The Debug Peripheral ID registers are:

Peripheral Identification Register 0

The EDPIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The EDPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 11.11.

Figure 11.12 shows the EDPIDR0 bit assignments.

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Table 11.17 shows the EDPIDR0 bit assignments.

Table 11.17. EDPIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] Part_0
0x03

Least significant byte of the debug part number.


The EDPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

Peripheral Identification Register 1

The EDPIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The EDPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 11.11.

Figure 11.13 shows the EDPIDR1 bit assignments.

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Table 11.18 shows the EDPIDR1 bit assignments.

Table 11.18. EDPIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0] Part_1
0xD

Most significant nibble of the debug part number.


The EDPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Peripheral Identification Register 2

The EDPIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The EDPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 11.11.

Figure 11.14 shows the EDPIDR2 bit assignments.

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Table 11.19 shows the EDPIDR2 bit assignments.

Table 11.19. EDPIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Revision
0x4

r0p4.

[3] JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0] DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


The EDPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Peripheral Identification Register 3

The EDPIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The EDPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 11.11.

Figure 11.15 shows the EDPIDR3 bit assignments.

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Table 11.20 shows the EDPIDR3 bit assignments.

Table 11.20. EDPIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] REVAND
0x0

Part minor revision.

[3:0] CMOD
0x0

Customer modified.


The EDPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Peripheral Identification Register 4

The EDPIDR4 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The EDPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 11.11.

Figure 11.16 shows the EDPIDR4 bit assignments.

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Table 11.21 shows the EDPIDR4 bit assignments.

Table 11.21. EDPIDR4 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.

[3:0] DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


The EDPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They are reserved for future use and are res0.

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