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Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. There is a set of eight registers, listed in register number order in Table 11.33.

Table 11.33. Summary of the ROM table Peripheral Identification Registers
Register Value Offset
ROMPIDR4 0x04 0xFD0
ROMPIDR5 0x00 0xFD4
ROMPIDR6 0x00 0xFD8
ROMPIDR7 0x00 0xFDC
ROMPIDR0 0xA1 0xFE0
ROMPIDR1 0xB4 0xFE4
ROMPIDR2 0x4B 0xFE8
ROMPIDR3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The ROM table Peripheral ID registers are:

Peripheral Identification Register 0

The ROMPIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The ROMPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 11.29.

Figure 11.23 shows the ROMPIDR0 bit assignments.

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Table 11.34 shows the ROMPIDR0 bit assignments.

Table 11.34. ROMPIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] Part_0

Least significant byte of the ROM table part number.

0xA1

For v8 memory map.

0xA3

For v7 memory map.


The ROMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

Peripheral Identification Register 1

The ROMPIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The ROMPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 11.29.

Figure 11.24 shows the ROMPIDR1 bit assignments.

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Table 11.35 shows the ROMPIDR1 bit assignments.

Table 11.35. ROMPIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] DES_0
0xB

Least significant nibble of JEP106 ID code. For ARM Limited.

[3:0] Part_1
0x4

Most significant nibble of the ROM table part number.


The ROMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Peripheral Identification Register 2

The ROMPIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The ROMPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 11.29.

Figure 11.25 shows the ROMPIDR2 bit assignments.

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Table 11.36 shows the ROMPIDR2 bit assignments.

Table 11.36. ROMPIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Revision
0x4

r0p4.

[3] JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0] DES_1
0b011

Designer, most significant bits of JEP106 ID code. For ARM Limited.


The ROMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Peripheral Identification Register 3

The ROMPIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The ROMPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 11.29.

Figure 11.26 shows the ROMPIDR3 bit assignments.

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Table 11.37 shows the ROMPIDR3 bit assignments.

Table 11.37. ROMPIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] REVAND
0x0

Part minor revision.

[3:0] CMOD
0x0

Customer modified.


The ROMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Peripheral Identification Register 4

The ROMPIDR4 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLK OSLK EDAD SLK Default
- - - - - RO

Table 11.1 describes the condition codes.

Configurations

The ROMPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 11.29.

Figure 11.27 shows the ROMPIDR4 bit assignments.

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Table 11.38 shows the ROMPIDR4 bit assignments.

Table 11.38. ROMPIDR4 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.

[3:0] DES_2
0x4

Designer, JEP106 continuation code, least significant nibble. For ARM Limited.


The ROMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They are reserved for future use and are res0.

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