Auxiliary Control Register
The TRCAUXCTLR characteristics are:
- Purpose
-
The function of this register is to provide implementation defined configuration and control options.
- Usage constraints
-
There are no usage constraints.
- Configurations
-
Available in all configurations.
- Attributes
-
See the register summary in Table 13.3.
Figure 13.7 shows the TRCAUXCTLR bit assignments.
Table 13.8 shows the TRCAUXCTLR bit assignments.
Bits | Name | Function |
---|---|---|
[31:8] | - | Reserved, res0. |
[7] |
COREIFEN |
Keep core interface enabled regardless of trace enable register state. The possible values are:
|
[6] | - |
Reserved, res0. |
[5] |
AUTHNOFLUSH |
Do not flush trace on de-assertion of authentication inputs. The possible values are:
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior. |
[4] |
TSNODELAY |
Do not delay timestamp insertion based on FIFO depth. The possible values are:
|
[3] |
SYNCDELAY |
Delay periodic synchronization if FIFO is more than half-full. The possible values are:
|
[2] |
OVFLW |
Force an overflow if synchronization is not completed when second synchronization becomes due. The possible values are:
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior. |
[1] |
IDLEACK |
Force idle-drain acknowledge high, CPU does not wait for trace to drain before entering WFX state. The possible values are:
When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior. |
[0] |
AFREADY |
Always respond to AFREADY immediately. Does not have any interaction with FIFO draining, even in WFI state. The possible values are:
|
The TRCAUXCTLR can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0x018
.