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Component Identification Registers

There are four read-only Component Identification Registers, Component ID0 to Component ID3. Table 13.73 shows these registers.

Table 13.73. Summary of the Component Identification Registers
Register Value Offset
Component ID0 0x0D 0xFF0
Component ID1 0x90 0xFF4
Component ID2 0x05 0xFF8
Component ID3 0xB1 0xFFC

The Component Identification Registers identify ETM trace unit as a CoreSight component.

The Component ID registers are:

Component Identification Register 0

The TRCCIDR0 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

See the register summary in Table 13.3.

Figure 13.70 shows the TRCCIDR0 bit assignments.

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Table 13.74 shows the TRCCIDR0 bit assignments.

Table 13.74. TRCCIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] PRMBL_0
0x0D

Preamble byte 0.


The TRCCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF0.

Component Identification Register 1

The TRCCIDR1 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

See the register summary in Table 13.3.

Figure 13.71 shows the TRCCIDR1 bit assignments.

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Table 13.75 shows the TRCCIDR1 bit assignments.

Table 13.75. TRCCIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0

[7:4] CLASS
0x9

Debug component

[3:0] PRMBL_1
0x0

Preamble byte 1


The TRCCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4.

Component Identification Register 2

The TRCCIDR2 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

See the register summary in Table 13.3.

Figure 13.72 shows the TRCCIDR2 bit assignments.

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Table 13.76 shows the TRCCIDR2 bit assignments.

Table 13.76. TRCCIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] PRMBL_2
0x05

Preamble byte 2.


The TRCCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8.

Component Identification Register 3

The TRCCIDR3 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

See the register summary in Table 13.3.

Figure 13.73 shows the TRCCIDR3 bit assignments.

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Table 13.77 shows the TRCCIDR3 bit assignments.

Table 13.77. TRCCIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] PRMBL_3
0xB1

Preamble byte 3.


The TRCCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC.

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