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Device Architecture Register

The TRCDEVARCH characteristics are:

Purpose

Identifies the ETM trace unit as an ETMv4 component.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.62 shows the TRCDEVARCH bit assignments.

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Table 13.64 shows the TRCDEVARCH bit assignments.

Table 13.64. TRCDEVARCH bit assignments
Bits Name Function
[31:21] ARCHITECT

Defines the architect of the component:

0x4

ARM JEP continuation.

0x3B

ARM JEP 106 code.

[20] PRESENT

Indicates the presence of this register:

0b1

Register is present.

[19:16] REVISION

Architecture revision:

0b0000

Architecture revision 0.

[15:0] ARCHID

Architecture ID:

0x4A13

ETMv4 component.


The TRCDEVARCH can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFBC.

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