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Event Control 1 Register

The TRCEVENTCTL1R characteristics are:


Controls the behavior of the events that TRCEVENTCTL0R selects

Usage constraints
  • You must always program this register as part of trace unit initialization.

  • Accepts writes only when the trace unit is disabled.


Available in all configurations.


TRCEVENTCTL1R is a 32-bit RW trace register.

See the register summary in Table 13.3.

Figure 13.9 shows the TRCEVENTCTL1R bit assignments.

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Table 13.10 shows the TRCEVENTCTL1R bit assignments.

Table 13.10. TRCEVENTCL1R bit assignments
Bits Name Function
[31:13] - Reserved, res0.

Low power state behavior override:


Low power state behavior unaffected.


Low power state behavior overridden. The resources and Event trace generation are unaffected by entry to a low power state.

[11] ATB

ATB trigger enable:


ATB trigger disabled.


ATB trigger enabled.

[10:4] - Reserved, res0.
[3:0] EN

One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:


Event does not cause an event element.


Event causes an event element.

The TRCEVENTCTL1R can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x024.

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