The TRCEVENTCTL1R characteristics are:
Controls the behavior of the events that TRCEVENTCTL0R selects
- Usage constraints
You must always program this register as part of trace unit initialization.
Accepts writes only when the trace unit is disabled.
Available in all configurations.
TRCEVENTCTL1R is a 32-bit RW trace register.
See the register summary in Table 13.3.
Figure 13.9 shows the TRCEVENTCTL1R bit assignments.
Table 13.10 shows the TRCEVENTCTL1R bit assignments.
Low power state behavior override:
ATB trigger enable:
One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:
The TRCEVENTCTL1R can be accessed through the internal memory-mapped
interface and the external debug interface, offset