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Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all CoreSight components. They are a set of eight registers, listed in register number order in Table 13.67.

Table 13.67. Summary of the Peripheral ID Registers
Register Value Offset
Peripheral ID4 0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0x5D 0xFE0
Peripheral ID1 0xB9 0xFE4
Peripheral ID2 0x4B 0xFE8
Peripheral ID3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The Peripheral ID registers are:

Peripheral Identification Register 0

The TRCPIDR0 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface, offset 0xFE0.

Configurations

Available in all implementations.

Attributes

TRCPIDR0 is a 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.65 shows the TRCPIDR0 bit assignments.

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Table 13.68 shows the TRCPIDR0 bit assignments.

Table 13.68. TRCPIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] Part_0
0x5D

Least significant byte of the ETM trace unit part number.


Peripheral Identification Register 1

The TRCPIDR1 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

TRCPIDR1 is a 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.66 shows the TRCPIDR1 bit assignments.

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Table 13.69 shows the TRCPIDR1 bit assignments.

Table 13.69. TRCPIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] DES_0
0xB

ARM Limited. This is bits[3:0] of JEP106 ID code.

[3:0] Part_1
0x9

Most significant four bits of the ETM trace unit part number.


The TRCPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Peripheral Identification Register 2

The TRCPIDR2 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

TRCPIDR2 is a 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.67 shows the TRCPIDR2 bit assignments.

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Table 13.70 shows the TRCPIDR2 bit assignments.

Table 13.70. TRCPIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Revision
0x4

r0p4.

[3] JEDEC
0b1

res1. Indicates a JEP106 identity code is used.

[2:0] DES_1
0b011

ARM Limited. This is bits[6:4] of JEP106 ID code.


The TRCPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Peripheral Identification Register 3

The TRCPIDR3 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

TRCPIDR3 is a 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.68 shows the TRCPIDR3 bit assignments.

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Table 13.71 shows the TRCPIDR3 bit assignments.

Table 13.71. TRCPIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] REVAND
0x0

Part minor revision.

[3:0] CMOD
0x0

Not customer modified.


The TRCPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Peripheral Identification Register 4

The TRCPIDR4 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

TRCPIDR4 is a 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.69 shows the TRCPIDR4 bit assignments.

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Table 13.72 shows the TRCPIDR4 bit assignments.

Table 13.72. TRCPIDR4 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.

[3:0] DES_2
0x4

ARM Limited. This is bits[3:0] of the JEP106 continuation code.


The TRCPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They are reserved for future use and are res0.

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