The TRCPDSR characteristics are:
Indicates the power down status of the ETM trace unit.
- Usage constraints
There are no usage constraints.
Available in all configurations.
See the register summary in Table 13.3.
Figure 13.45 shows the TRCPDSR bit assignments.
Table 13.46 shows the TRCPDSR bit assignments.
OS lock status.
Sticky power down state.
This bit is set to 1 when power to the ETM trace unit registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.
Indicates the ETM trace unit is powered:
If a system implementation allows the ETM trace unit to be powered off independently of the debug power domain, the system must handle accesses to the ETM trace unit appropriately.
The TRCPDSR can be accessed through the internal memory-mapped
interface and the external debug interface, offset