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Single-Shot Comparator Control Register 0

The TRCSSCCR0 characteristics are:

Purpose

Controls the single-shot comparator.

Usage constraints

Accepts writes only when the trace unit is disabled.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.40 shows the TRCSSCCR0 bit assignments.

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Table 13.41 shows the TRCSSCCR0 bit assignments.

Table 13.41. TRCSSCCR0 bit assignments
Bits Name Function
[31:25] - Reserved, res0.
[24] RST

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:

1

Reset enabled. Multiple matches can occur.

[23:20] - Reserved, res0.
[19:16] ARC

Selects one or more address range comparators for single-shot control.

One bit is provided for each implemented address range comparator.

[15:8] - Reserved, res0.
[7:0] SAC

Selects one or more single address comparators for single-shot control.

One bit is provided for each implemented single address comparator.


The TRCSSCCR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x280.

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