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ViewInst Main Control Register

The TRCVICTLR characteristics are:

Purpose

Controls instruction trace filtering.

Usage constraints
  • Accepts writes only when the trace unit is disabled.

  • Returns stable data only when TRCSTATR.PMSTABLE==1.

  • Must be programmed, particularly to set the value of the SSSTATUS bit, that sets the state of the start-stop logic.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.15 shows the TRCVICTLR bit assignments.

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Table 13.16 shows the TRCVICTLR bit assignments.

Table 13.16. TRCVICTLR bit assignments
Bits Name Function
[31:24] - Reserved, res0.
[23:20] EXLEVEL_NS

In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level:

0

Trace unit generates instruction trace, in Non-secure state, for exception level n.

1

Trace unit does not generate instruction trace, in Non-secure state, for exception level n.

Note

The exception levels are:

Bit[20]

Exception level 0.

Bit[21]

Exception level 1.

Bit[22]

Exception level 2.

Bit[23]

RAZ/WI. Instruction tracing is not implemented for exception level 3.

[19:16] EXLEVEL_S

In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level:

0

Trace unit generates instruction trace, in Secure state, for exception level n.

1

Trace unit does not generate instruction trace, in Secure state, for exception level n.

Note

The exception levels are:

Bit[16]

Exception level 0.

Bit[17]

Exception level 1.

Bit[18]

RAZ/WI. Instruction tracing is not implemented for exception level 2.

Bit[19]

Exception level 3.

[15:12] - Reserved, res0.
[11] TRCERR

Selects whether a system error exception must always be traced:

0

System error exception is traced only if the instruction or exception immediately before the system error exception is traced.

1

System error exception is always traced regardless of the value of ViewInst.

[10] TRCRESET

Selects whether a reset exception must always be traced:

0

Reset exception is traced only if the instruction or exception immediately before the reset exception is traced.

1

Reset exception is always traced regardless of the value of ViewInst.

[9] SSSTATUS

Indicates the current status of the start/stop logic:

0

Start/stop logic is in the stopped state.

1

Start/stop logic is in the started state.

[8] - Reserved, res0.
[7] TYPE

Selects the resource type for the viewinst event:

0

Single selected resource.

1

Boolean combined resource pair.

[6:4] - Reserved, res0.
[3:0] SEL

Selects the resource number to use for the viewinst event, based on the value of TYPE:

When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].


The TRCVICTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x080.

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