ETM register summary
This section summarizes the ETM trace unit registers. For full descriptions of the ETM trace unit registers, see:
-
ETM register descriptions, for the implementation defined registers and the ARM® ETM Architecture Specification, ETMv4, for the other registers.
Note
In Table 13.3, access type is described as follows:
- RW
-
Read and write.
- RO
-
Read only.
- WO
-
Write only.
Table 13.3 lists all of the ETM trace unit registers.
All ETM trace unit registers are 32 bits wide. The description of each register includes its offset from a base address. The base address is defined by the system integrator when placing the ETM trace unit in the Debug-APB memory map.