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ETM register summary

This section summarizes the ETM trace unit registers. For full descriptions of the ETM trace unit registers, see:

  • ETM register descriptions, for the implementation defined registers and the ARM® ETM Architecture Specification, ETMv4, for the other registers.


In Table 13.3, access type is described as follows:


Read and write.


Read only.


Write only.

Table 13.3 lists all of the ETM trace unit registers.

All ETM trace unit registers are 32 bits wide. The description of each register includes its offset from a base address. The base address is defined by the system integrator when placing the ETM trace unit in the Debug-APB memory map.

Table 13.3. ETM trace unit register summary
Name Type Description
- - Reserved

Programming Control Register

TRCSTATR RO Status Register
TRCCONFIGR RW Trace Configuration Register
TRCAUXCTLR RW Auxiliary Control Register
TRCEVENTCTL0R RW Event Control 0 Register
TRCEVENTCTL1R RW Event Control 1 Register
TRCSTALLCTLR RW Stall Control Register
TRCTSCTLR RW Global Timestamp Control Register
TRCSYNCPR RW Synchronization Period Register
TRCCCCTLR RW Cycle Count Control Register
TRCBBCTLR RW Branch Broadcast Control Register
TRCVICTLR RW ViewInst Main Control Register
TRCVIIECTLR RW ViewInst Include-Exclude Control Register
TRCVISSCTLR RW ViewInst Start-Stop Control Register
TRCSEQEVR0 RW Sequencer State Transition Control Registers 0-2
TRCSEQEVR1 RW Sequencer State Transition Control Registers 0-2
TRCSEQEVR2 RW Sequencer State Transition Control Registers 0-2
TRCSEQRSTEVR RW Sequencer Reset Control Register
TRCSEQSTR RW Sequencer State Register
TRCEXTINSELR RW External Input Select Register
TRCCNTRLDVR0 RW Counter Reload Value Registers 0-1
TRCCNTRLDVR1 RW Counter Reload Value Registers 0-1
TRCCNTCTLR0 RW Counter Control Register 0
TRCCNTCTLR1 RW Counter Control Register 1
TRCCNTVR0 RW Counter Value Registers 0-1
TRCCNTVR1 RW Counter Value Registers 0-1
TRCIDR8 RO ID Register 8
TRCIDR9 RO ID Register 9
TRCIDR10 RO ID Register 10
TRCIDR11 RO ID Register 11
TRCIDR12 RO ID Register 12
TRCIDR13 RO ID Register 13
TCRIMSPEC0 RW Implementation Specific Register 0
TRCIDR0 RO ID Register 0
TRCIDR1 RO ID Register 1
TRCIDR2 RO ID Register 2
TRCIDR3 RO ID Register 3
TRCIDR4 RO ID Register 4
TRCIDR5 RO ID Register 5
TRCRSCTLRn RW Resource Selection Control Registers 2-16, n is 2, 15
TRCSSCCR0 RW Single-Shot Comparator Control Register 0
TRCSSCSR0 RW, RO Single-Shot Comparator Status Register 0
TRCOSLAR WO OS Lock Access Register
TRCOSLSR RO OS Lock Status Register
TRCPDCR RW Power Down Control Register
TRCPDSR RO Power Down Status Register
TRCACVRn RW Address Comparator Value Registers 0-7
TRCACATRn RW Address Comparator Access Type Registers 0-7
TRCCIDCVR0 RW Context ID Comparator Value Register 0
TRCVMIDCVR0 RW VMID Comparator Value Register 0
TRCCIDCCTLR0 RW Context ID Comparator Control Register 0
TRCITATBIDR RW Integration ATB Identification Register
TRCITIDATAR WO Integration Instruction ATB Data Register
TRCITIATBINR RO Integration Instruction ATB In Register
TRCITIATBOUTR WO Integration Instruction ATB Out Register
TRCITCTRL RW Integration Mode Control Register
TRCCLAIMSET RW Claim Tag Set Register
TRCCLAIMCLR RW Claim Tag Clear Register
TRCDEVAFF0 RO Device Affinity Register 0
TRCDEVAFF1 RO Device Affinity Register 1
TRCLAR WO Software Lock Access Register
TRCLSR RO Software Lock Status Register
TRCAUTHSTATUS RO Authentication Status Register
TRCDEVARCH RO Device Architecture Register
TRCDEVID RO Device ID Register
TRCDEVTYPE RO Device Type Register
TRCPIDR4 RO Peripheral Identification Register 4
TRCPIDR5 RO Peripheral Identification Register 5-7
TRCPIDR0 RO Peripheral Identification Register 0
TRCPIDR1 RO Peripheral Identification Register 1
TRCPIDR2 RO Peripheral Identification Register 2
TRCPIDR3 RO Peripheral Identification Register 3
TRCCIDR0 RO Component Identification Register 0
TRCCIDR1 RO Component Identification Register 1
TRCCIDR2 RO Component Identification Register 2
TRCCIDR3 RO Component Identification Register 3