The Instruction Fetch Unit (IFU) contains the instruction cache controller and its associated linefill buffer. The Cortex-A53 MPCore instruction cache is 2-way set associative and uses Virtually Indexed Physically Tagged (VIPT) cache lines holding up to 16 A32 instructions, 16 32-bit T32 instructions, 16 A64 instructions, or up to 32 16-bit T32 instructions.
The IFU cannot hold A64, A32, and T32 instructions in the same cache line. For example, if the IFU fetches both A32 and T32 instructions from the same 64 byte region of memory, that region occupies two cache lines, one for the A32 instructions and one for the T32 instructions.
The instruction cache has the following features:
Pseudo-random cache replacement policy.
Sequential instruction fetches.
Critical word first linefill on a cache miss.
The IFU obtains instructions from the instruction cache or from external memory and predicts the outcome of branches in the instruction stream, then passes the instructions to the Data Processing Unit (DPU) for processing.
If the cache protection configuration is chosen, the L1 Instruction cache data and tag RAMs are protected by parity bits. The parity bits enable any single-bit error to be detected. If an error is detected, the line is invalidated and fetched again.
- Branch Target Instruction Cache
The IFU contains a single entry Branch Target Instruction Cache (BTIC). This stores up to two instruction cache fetches and enables the branch shadow of predicted taken branch instructions to be eliminated. The BTIC implementation is architecturally transparent, so it does not have to be flushed on a context switch.
- Branch Target Address Cache
The IFU contains a 256-entry Branch Target Address Cache (BTAC) to predict the target address of indirect branches. The BTAC implementation is architecturally transparent, so it does not have to be flushed on a context switch.
- Branch predictor
The branch predictor is a global type that uses branch history registers and a 3072-entry pattern history prediction table.
- Return stack
The IFU includes an 8-entry return stack to accelerate returns from procedure calls. For each procedure call, the return address is pushed onto a hardware stack. When a procedure return is recognized, the address held in the return stack is popped, and the IFU uses it as the predicted return address. The return stack is architecturally transparent, so it does not have to be flushed on a context switch.
See Level 1 Memory System for more information.