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Clocks

The Cortex-A53 processor has a single clock input, CLKIN. All cores in the Cortex-A53 processor and the SCU are clocked with a distributed version of CLKIN.

The Cortex-A53 processor has the following clock enable signals:

PCLKENDBG

The processor includes an APB interface to access the debug and performance monitoring registers. Internally this interface is driven from CLKIN. A separate enable signal, PCLKENDBG, is provided to enable the external APB bus to be driven at a lower frequency, that must be an integer ratio of CLKIN. If the debug infrastructure in the system is required to be fully asynchronous to the processor clock, you can use a synchronizing component to connect the external AMBA APB to the processor.

Figure 2.2 shows a timing example of PCLKENDBG that changes the CLKIN to PCLK frequency ratio from 3:1 to 1:1.

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Note

Figure 2.2 shows the timing relationship between the debug APB clock, PCLK and PCLKENDBG, where PCLKENDBG asserts one clock cycle before the rising edge of PCLK. It is important that the relationship between PCLK and PCLKENDBG is maintained.

ACLKENM

This signal is present only if the master interface is configured to use the ACE protocol. The master interface supports integer ratios of the CLKIN frequency, for example 1:1, 2:1, 3:1. These ratios are configured through external clock enable signals. In all cases AXI transfers remain synchronous. The ACE master interface includes the ACLKENM clock enable signal.

ACLKENM asserts one CLKIN cycle before the rising edge of the external ACE clock signal, ACLKM. If you change the CLKIN to ACLKM frequency ratio, you must change ACLKENM correspondingly.

Figure 2.3 shows a timing example of ACLKENM that changes the CLKIN to ACLKM frequency ratio from 3:1 to 1:1.

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Note

  • Figure 2.3 shows the timing relationship between the AXI master clock, ACLKM and ACLKENM, where ACLKENM asserts one clock cycle before the rising edge of ACLKM. It is important that the relationship between ACLKM and ACLKENM is maintained.

  • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted.

  • The input signal ACLKENM exists in the Cortex-A53 processor if it is configured to include the ACE interface.

ACLKENS

This signal is present only if the processor is configured with the ACP slave interface. The slave interface supports integer ratios of the CLKIN frequency, for example 1:1, 2:1, 3:1. These ratios are configured through external clock enable signals. In all cases AXI transfers remain synchronous. The ACP slave interface includes the ACLKENS clock enable signal.

ACLKENS asserts one CLKIN cycle before the rising edge of the external ACP clock signal, ACLKS. If you change the CLKIN to ACLKS frequency ratio, you must change ACLKENS correspondingly.

Figure 2.4 shows a timing example of ACLKENS that changes the CLKIN to ACLKS frequency ratio from 3:1 to 1:1.

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Note

  • Figure 2.4 shows the timing relationship between the AXI slave clock, ACLKS and ACLKENS, where ACLKENS asserts one clock cycle before the rising edge of ACLKS. It is important that the relationship between ACLKS and ACLKENS is maintained.

  • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted.

  • The input signal ACLKENS exists in the Cortex-A53 processor if it is configured to include the ACP interface.

SCLKEN

This signal is present only if the master interface is configured to use the CHI protocol. The SCU interface supports integer ratios of the CLKIN frequency, for example 1:1, 2:1, 3:1. These ratios are configured through external clock enable signals. In all cases CHI transfers remain synchronous. The CHI master interface includes the SCLKEN clock enable signal.

Figure 2.5 shows a timing example of SCLKEN that changes the CLKIN to SCLK frequency ratio from 3:1 to 1:1.

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Note

  • Figure 2.5 shows the timing relationship between the CHI clock, SCLK and SCLKEN, where SCLKEN asserts one CLKIN cycle before the rising edge of SCLK. It is important that the relationship between SCLK and SCLKEN is maintained.

  • If there are any physical effects that could occur while changing the clock frequency, ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted.

  • The input signal SCLKEN exists in the Cortex-A53 processor if it is configured to include the CHI interface.

ATCLKEN

The ATB interface is a synchronous interface that can operate at any integer multiple that is equal to or slower than the main processor clock, CLKIN, using the ATCLKEN signal. For example, the CLKIN to ATCLK frequency ratio can be 1:1, 2:1, or 3:1, where ATCLK is the ATB bus clock. ATCLKEN asserts one CLKIN cycle before the rising edge of ATCLK. If you change the CLKIN to ATCLK frequency ratio, you must change ATCLKEN correspondingly.

Figure 2.6 shows a timing example of ATCLKEN that changes the CLKIN to ATCLK frequency ratio from 3:1 to 1:1.

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Note

Figure 2.6 shows the timing relationship between the ATB clock, ATCLK and ATCLKENDBG, where ATCLKENDBG asserts one clock cycle before the rising edge of ATCLK. It is important that the relationship between ATCLK and ATCLKENDBG is maintained.

CNTCLKEN

The CNTVALUEB is a synchronous 64-bit binary encoded counter value that can operate at any integer multiple that is equal to or slower than the main processor clock, CLKIN, using the CNTCLKEN signal. For example, you can set the CLKIN to CNTCLK frequency ratio to 1:1, 2:1, or 3:1, where CNTCLK is the system counter clock. CNTCLKEN asserts one CLKIN cycle prior to the rising edge of CNTCLK.

Figure 2.7 shows a timing example of CNTCLKEN that changes the CLKIN to CNTCLK frequency ratio from 3:1 to 1:1.

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Note

Figure 2.7 shows the timing relationship between the system counter clock, CLKIN and CNTCLKEN, where CNTCLKEN asserts one clock cycle before the rising edge of CLKIN. It is important that the relationship between CLKIN and CNTCLKEN is maintained.

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