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Resets

The Cortex-A53 processor has the following active-LOW reset input signals:

nCPUPORESET[CN:0]

Where CN is the number of cores minus one.

These primary, cold reset signals initialize all resettable registers in the corresponding core, including debug registers and ETM registers.

nCORERESET[CN:0]

These primary reset signals initialize all resettable registers in the corresponding core, not including debug registers and ETM registers.

nPRESETDBG

This single, cluster-wide signal resets the integrated CoreSight components that connect to the external PCLK domain, such as debug logic.

nL2RESET

This single, cluster-wide signal resets all resettable registers in the L2 memory system and the logic in the SCU.

nMBISTRESET

An external MBIST controller can use this signal to reset the entire SoC. The nMBISTRESET signal resets all resettable registers in the cluster, for entry into, and exit from, MBIST mode.

All of these resets can be asynchronously:

  • Asserted, HIGH to LOW.

  • Deasserted, LOW to HIGH.

Reset synchronisation logic inside the Cortex-A53 processor ensures that reset deassertion is synchronous for all resettable registers. The processor clock is not required for reset assertion, but the processor clock must be present for reset deassertion to ensure reset synchronisation.

In general, you only have to hold reset signals active for three processor clock cycles for the reset to take effect. However, you must hold the reset signal LOW until the power returns and the unit or processor is ready for the reset to take effect if:

  • The Advanced SIMD and Floating-point unit of a core undergoing a reset is in retention state.

  • A core that is being reset is in retention state.

This is the responsibility of the system implementer, because the time taken for retention exit and the behavior of the power controller varies by partner and by implementation.

Table 2.1 describes the valid reset signal combinations. All other combinations of reset signals are illegal. In the table, n designates the core that is reset.

Table 2.1. Valid reset combinations
Reset combination Signals Value Description
Cluster cold reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0[a]

all = X[a]

0

0

1

All logic is held in reset.
Cluster cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0[a]

all = X[a]

1

0

1

All cores are held in reset so they can be powered up. The L2 is held in reset, but must remain powered up. This enables external debug over power down for the cluster.

Individual core cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 0[a]

[n] = X[a]

1

1

1

Individual core is held in reset, so that the core can be powered up. This enables external debug over power down for the core that is held in reset.
Individual core warm reset with trace and debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 1

[n] = 0

1

1

1

Individual core is held in reset.
Debug logic reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

0

1

1

Cluster debug logic is held in reset.
MBIST reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

0

All logic is held in reset.
Normal state

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

1

No logic is held in reset.

[a] For cold reset, nCPUPORESET must be asserted. nCORERESET can be asserted, but is not required.


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