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Power domains

Table 2.2 shows the power domains that the Cortex-A53 processor supports:

Table 2.2. Power domain description
Power domain Description

This includes the SCU, the optional L2 cache controller, and debug registers described as being in the debug domain.


This includes the L2 data RAM, L2 tag RAM, L2 victim RAM, and the SCU duplicate tag RAM.


This includes the optional Advanced SIMD and Floating-point Extension, the L1 TLB, L1 processor RAMs, and debug registers described as being in the processor domain.

PDCPUADVSIMD<n[a]> This represents the Advanced SIMD and Floating-point block of core n.

[a] <n> where n is 0, 1, 2, or 3. This represents core 0, core 1, core 2, or core 3. If a core is not present, the corresponding Power Domain is not present.

The separate PDCORTEXA53 and PDL2 power domains can remain active even when all the cores are powered down. This means the Cortex-A53 processor can continue to accept snoops from external devices to access the L2 cache.

Figure 2.8 shows an example of the domains embedded in a System-on-Chip (SoC) power domain.

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