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Power modes

The power domains can be controlled independently to give different combinations of powered-up and powered-down domains. However, only some powered-up and powered-down domain combinations are valid and supported.

Table 2.4 and Table 2.5 show the supported power domain states for the Cortex-A53 processor. The terms used are defined in Table 2.3.

Table 2.3. Power state description
Power state Description
Off Block is power gated
Ret Logic or RAM retention power only
On Block is active

Caution

States not shown in Table 2.4 and Table 2.5 are unsupported and must not occur.

Table 2.4. Supported processor power states
Power domains Description
PDCORTEXA53 PDL2 PDCPU<n>
Off Off Off Processor off.
Off On/Ret Off L2 Cache Dormant Mode.
On Ret See Table 2.5

Processor On, L2 RAMs Retained.

All cores either off or in WFx.

Note

L2 RAM Retention Entry or Residency Condition.

On Ret See Table 2.5

Processor On, L2 RAMs Retained.

At least one core running.

Note

Transient Condition.

On On See Table 2.5 Processor On, SCU/L2 RAMs Active.

Table 2.5 describes the supported power domain states for individual cores. The power domain state in each core is independent of all other cores.

Table 2.5. Supported core power states
Power domains Description
PDCPU PDADVSIMD
Off Off Core off.
On On Core on. Advanced SIMD and Floating-point on.
On Ret AdvSIMD retention. Advanced SIMD and Floating-point in retention.
Ret Ret Core retention. Core logic and Advanced SIMD and Floating-point in retention.

You must follow the dynamic power management and powerup and powerdown sequences described in the following sections. Any deviation from these sequences can lead to unpredictable results.

The supported power modes are:

Normal state

This is the normal mode of operation where all of the processor functionality is available. The Cortex-A53 processor uses gated clocks and gates to disable inputs to unused functional blocks. Only the logic in use to perform an operation consumes any dynamic power.

Standby state

The following sections describe the methods of entering standby state:

Core Wait for Interrupt

Wait for Interrupt is a feature of the ARMv8-A architecture that puts the core in a low-power state by disabling most of the clocks in the core while keeping the core powered up. Apart from a small dynamic power overhead on the logic to enable the core to wake up from WFI low-power state, this reduces the power drawn to static leakage current only.

Software indicates that the core can enter the WFI low-power state by executing the WFI instruction.

When the core is executing the WFI instruction, the core waits for all instructions in the core to retire before entering the idle or low power state. The WFI instruction ensures that all explicit memory accesses, that occurred before the WFI instruction in program order, have retired. For example, the WFI instruction ensures that the following instructions received the required data or responses from the L2 memory system:

  • Load instructions.

  • Cache and TLB maintenance operations.

  • Store exclusive instructions.

In addition, the WFI instruction ensures that store instructions have updated the cache or have been issued to the SCU.

While the core is in WFI low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFI low-power state, when any of the following events are detected:

  • A snoop request that must be serviced by the core L1 Data cache.

  • A cache or TLB maintenance operation that must be serviced by the core L1 Instruction cache, data cache, or TLB.

  • An APB access to the debug or trace registers residing in the core power domain.

Exit from WFI low-power state occurs when the core detects a reset or one of the WFI wake up events as described in the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

On entry into WFI low-power state, STANDBYWFI for that core is asserted. Assertion of STANDBYWFI guarantees that the core is in idle and low power state. STANDBYWFI continues to assert even if the clocks in the core are temporarily enabled because of an L2 snoop request, cache, or TLB maintenance operation or an APB access.

Note

STANDBYWFI does not indicate completion of L2 memory system transactions initiated by the processor. All Cortex-A53 processor implementations contain an L2 memory system. This includes implementations without an L2 cache.

Core Wait for Event

Wait for Event (WFE) is a feature of the ARMv8-A architecture that can be used by a locking mechanism based on events to put the core in a low power state by disabling most of the clocks in the core while keeping the core powered up. Apart from a small dynamic power overhead on the logic to enable the core to wake up from WFE low-power state, this reduces the power drawn to static leakage current only.

A core enters into WFE low-power state by executing the WFE instruction. When executing the WFE instruction, the core waits for all instructions in the core to complete before entering the idle or low power state.

If the event register is set, execution of WFE does not cause entry into standby state, but clears the event register.

While the core is in WFE low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFE low-power state, when any of the following events are detected:

  • An L2 snoop request that must be serviced by the core L1 Data cache.

  • A cache or TLB maintenance operation that must be serviced by the core L1 Instruction cache, data cache, or TLB.

  • An APB access to the debug or trace registers residing in the core power domain.

Exit from WFE low-power state occurs when the core detects a reset, the assertion of the EVENTI input signal, or one of the WFE wake up events as described in the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

On entry into WFE low-power state, STANDBYWFE for that core is asserted. Assertion of STANDBYWFE guarantees that the core is in idle and low power state. STANDBYWFE continues to assert even if the clocks in the core are temporarily enabled because of an L2 snoop request, cache, and TLB maintenance operation or an APB access.

CLREXMON request and acknowledge signaling

When the CLREXMONREQ input is asserted, it signals the clearing of an external global exclusive monitor and acts as WFE wake-up event to all the cores in the cluster.

The CLREXMONREQ signal has a corresponding CLREXMONACK response signal. This forms a standard 2-wire, 4-phase handshake that can be used to signal across the voltage and frequency boundary between the core and system.

Figure 2.9 shows the CLREXMON request and acknowledge handshake. When the request signal is asserted, it continues to assert until an acknowledge is received. When the request is deasserted, the acknowledge can then deassert.

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Wait for Interrupt

When all the cores are in WFI low-power state, the shared L2 memory system logic that is common to all the cores can also enter a WFI low-power state.

Entry into L2 WFI low-power state can occur only if specific requirements are met and the following sequence applied:

  • All cores are in WFI low-power state and therefore, the STANDBYWFI output for each core is asserted. Assertion of all the cores STANDBYWFI outputs guarantee that all the cores are in idle and low power state. All clocks in the cores, with the exception of a small amount of clock wake up logic, are disabled.

  • If configured with ACE, the SoC asserts the input pin ACINACTM to idle the AXI master interface. This indicates that no snoop requests will be made from the external memory system.

  • If configured with a CHI interface, the SoC asserts the input pin SINACT to idle the CHI master interface. This indicates that no snoop requests will be made from the external memory system.

  • If configured with an ACP interface, the SoC asserts the AINACTS input pin to idle the ACP interface. This indicates that the SoC sends no more transaction on the ACP interface.

When the L2 memory system completes the outstanding transactions for AXI or CHI interfaces, it can then enter the low power state, L2 WFI low-power state. On entry into L2 WFI low-power state, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2 memory system is idle and does not accept new transactions.

Exit from L2 WFI low-power state occurs on one of the following events:

  • A physical IRQ or FIQ interrupt.

  • A debug event.

  • Powerup or warm reset.

When a core exits from WFI low-power state, STANDBYWFI for that core is deasserted. When the L2 memory system logic exits from WFI low-power state, STANDBYWFIL2 is deasserted. The SoC must continue to assert ACINACTM or SINACT until STANDBYWFIL2 has deasserted.

Figure 2.10 shows the L2 WFI timing for a 4-core configuration.

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Individual core shutdown mode

In this mode, the PDCPU power domain for an individual core is shut down and all state is lost.

For full shutdown of the Cortex-A53 processor, including implementations with a single core, see Cluster shutdown mode without system driven L2 flush and Cluster shutdown mode with system driven L2 flush.

To enable a core to be powered down, the implementation must place the core on a separately controlled power supply. In addition, you must clamp the outputs of the core to benign values while the entire cluster is powered down, to indicate that the core is idle.

To power down the core, apply the following sequence:

  1. Disable the data cache, by clearing the SCTLR.C bit, or the HSCTLR.C bit if in Hyp mode. This prevents more data cache allocations and causes cacheable memory attributes to change to Normal Non-cacheable. Subsequent loads and stores do not access the L1 or L2 caches.

  2. Clean and invalidate all data from the L1 Data cache. The L2 duplicate snoop tag RAM for this core is now empty. This prevents any new data cache snoops or data cache maintenance operations from other cores in the cluster being issued to this core.

  3. Disable data coherency with other cores in the cluster, by clearing the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the core to be taken out of coherency by preventing the core from receiving cache or TLB maintenance operations broadcast by other cores in the cluster.

  4. Execute an ISB instruction to ensure that all of the register changes from the previous steps have been committed.

  5. Execute a DSB SY instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any core in the cluster device before the SMPEN bit was cleared have completed.

  6. Execute a WFI instruction and wait until the STANDBYWFI output is asserted to indicate that the core is in idle and low power state.

  7. Deassert DBGPWRDUP LOW. This prevents any external debug access to the core.

  8. Activate the core output clamps.

  9. Assert nCPUPORESET LOW

  10. Remove power from the PDCPU power domain.

To power up the core, apply the following sequence:

  1. Assert nCPUPORESET LOW. Ensure DBGPWRDUP is held LOW to prevent any external debug access to the core.

  2. Apply power to the PDCPU power domain. Keep the state of the signals nCPUPORESET and DBGPWRDUP LOW.

  3. Release the core output clamps.

  4. Deassert resets.

  5. Set the SMPEN bit to 1 to enable snooping into the core.

  6. Assert DBGPWRDUP HIGH to allow external debug access to the core.

  7. If required use software to restore the state of the core as it was prior to powerdown.

Cluster shutdown mode without system driven L2 flush

This is the mode where the PDCORTEXA53, PDL2, and PDCPU power domains are shut down and all state is lost. In this section, a lead core is defined as the last core to switch off, or the first core to switch on. To power down the cluster, apply the following sequence:

  1. Ensure all non-lead cores are in shutdown mode, see Individual core shutdown mode.

  2. Follow steps 1 to 2 in Individual core shutdown mode.

  3. If the ACP interface is configured, ensure that any master connected to the interface does not send new transactions, then assert AINACTS.

  4. Clean and invalidate all data from the L2 Data cache.

  5. Follow steps 3 to 10 in Individual core shutdown mode.

  6. In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert SINACT. Then wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle. All Cortex-A53 processor implementations contain an L2 memory system, including implementations without an L2 cache.

  7. Activate the cluster output clamps.

  8. Remove power from the PDCORTEXA53 and PDL2 power domains.

Note

For device powerdown, all operations on the lead core must occur after the equivalent step on all non-lead cores.

To power up the cluster, apply the following sequence:

  1. For each core in the cluster, assert nCPUPORESET LOW.

  2. Assert nL2RESET LOW and hold L2RSTDISABLE LOW.

  3. Apply power to the PDCORTEXA53 and PDL2 domains while keeping the signals described in steps 1. and 2. LOW.

  4. Release the cluster output clamps.

  5. Continue a normal cold reset sequence.

Cluster shutdown mode with system driven L2 flush

This is the mode where the PDCORTEXA53, PDL2, and PDCPU power domains are shut down and all state is lost. To power down the cluster, apply the following sequence:

  1. Ensure all cores are in shutdown mode, see Individual core shutdown mode.

  2. The SoC asserts the AINACTS signal to idle the ACP. This is necessary to prevent ACP transactions from allocating new entries in the L2 cache while the hardware cache flush is occurring.

  3. Assert L2FLUSHREQ HIGH.

  4. Hold L2FLUSHREQ HIGH until L2FLUSHDONE is asserted.

  5. Deassert L2FLUSHREQ.

  6. In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert SINACT. Then wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle. All Cortex-A53 processor implementations contain an L2 memory system, including implementations without an L2 cache.

  7. Activate the cluster output clamps.

  8. Remove power from the PDCORTEXA53 and PDL2 power domains.

Note

For device powerdown, all operations on a lead core must occur after the equivalent step on all non-lead cores.

To power up the cluster, apply the following sequence:

  1. For each core in the cluster, assert nCPUPORESET LOW.

  2. Assert nL2RESET LOW and hold L2RSTDISABLE LOW.

  3. Apply power to the PDCORTEXA53 and PDL2 domains while keeping the signals described in steps 1 and 2 LOW.

  4. Release the cluster output clamps.

  5. Continue a normal cold reset sequence.

Dormant mode

Optionally, the Dormant mode is supported in the cluster. In this mode all the cores and L2 control logic are powered down while the L2 cache RAMs are powered up and retain state. The RAM blocks that remain powered up during Dormant mode are:

  • L2 tag RAMs.

  • L2 data RAMs.

  • L2 victim RAM.

To support Dormant mode, you must ensure:

  • That the L2 cache RAMs are in a separate power domain.

  • To clamp all inputs to the L2 cache RAMs to benign values. This avoids corrupting data when the cores and L2 control power domains enter and exit power down state.

Before entering Dormant mode the architectural state of the cluster, excluding the contents of the L2 cache RAMs that remain powered up, must be saved to external memory.

As part of the exit from Dormant mode to Normal state, the SoC must perform a cold reset sequence. The SoC must assert the reset signals until power is restored. After power is restored, the cluster exits the cold reset sequence, and the architectural state must be restored.

To enter Dormant mode, apply the following sequence:

  1. Disable the data cache, by clearing the SCTLR.C bit, or the HSCTLR.C bit if in Hyp mode. This prevents more data cache allocations and causes cacheable memory attributes to change to Normal Non-cacheable. Subsequent loads and stores do not access the L1 or L2 caches.

  2. Clean and invalidate all data from the L1 Data cache. The L2 duplicate snoop tag RAM for this core is now empty. This prevents any new data cache snoops or data cache maintenance operations from other cores in the cluster being issued to this core.

  3. Disable data coherency with other cores in the cluster, by clearing the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the core to be taken out of coherency by preventing the core from receiving cache or TLB maintenance operations broadcast by other cores in the cluster.

  4. Save architectural state, if required. These state saving operations must ensure that the following occur:

    • All ARM registers, including the CPSR and SPSR, are saved.

    • All system registers are saved.

    • All debug related state is saved.

  5. Execute an ISB instruction to ensure that all of the register changes from the previous steps have been committed.

  6. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any core in the cluster before the SMPEN bit was cleared have completed. In addition, this ensures that all state saving has completed.

  7. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicate that the core is in idle and low power state.

  8. Repeat the previous steps for all cores, and wait for all STANDBYWFI outputs to be asserted.

  9. If the ACP interface is configured, ensure that any master connected to the interface does not send new transactions, then assert AINACTS.

  10. If ACE is implemented, the SoC asserts the input pin ACINACTM to idle the AXI master interface after all snoop transactions have been sent on the interface. If CHI is implemented, the SoC asserts the input pin SINACT.

    When the L2 has completed the outstanding transactions for the AXI master and slave interfaces, STANDBYWFIL2 is asserted to indicate that L2 memory system is idle. All Cortex-A53 processor implementations contain an L2 memory system, including implementations without an L2 cache.

  11. When all cores STANDBYWFI and STANDBYWFIL2 are asserted, the cluster is ready to enter Dormant mode.

  12. Activate the L2 cache RAM input clamps.

  13. Remove power from the PDCPU and PDCORTEXA53 power domains.

To exit Dormant mode, apply the following sequence:

  1. Apply a normal cold reset sequence. You must apply resets to the cores and the L2 memory system logic until power is restored. During this reset sequence, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.

  2. When power has been restored, release the L2 cache RAM input clamps.

  3. Continue a normal cold reset sequence with L2RSTDISABLE held HIGH.

  4. The architectural state must be restored, if required.

Retention state

Contact ARM for information about retention state.

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