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Virtual interface control register summary

The virtual interface control registers are management registers. Configuration software on the Cortex-A53 processor must ensure they are accessible only by a hypervisor, or similar software.

Table 9.5 describes the registers for the virtual interface control registers.

All the registers in Table 9.5 are word-accessible. Registers not described in this table are res0. See the ARM® Generic Interrupt Controller Architecture Specification for more information.

Table 9.5. Virtual interface control register summary
Name Type Reset Description
GICH_HCR RW 0x00000000 Hypervisor Control Register
GICH_VTR RO 0x90000003 VGIC Type Register
GICH_VMCR RW 0x004C0000

Virtual Machine Control Register

GICH_MISR RO 0x00000000

Maintenance Interrupt Status Register

GICH_EISR0 RO 0x00000000

End of Interrupt Status Registers

GICH_ELRSR0 RO 0x0000000F

Empty List Register Status Registers

GICH_APR0 RW 0x00000000 Active Priorities Register
GICH_LR0 RW 0x00000000 List Register 0
GICH_LR1 RW 0x00000000 List Register 1
GICH_LR2 RW 0x00000000 List Register 2
GICH_LR3 RW 0x00000000 List Register 3

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