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AArch32 Generic Timer register summary

Table 10.3 shows the AArch32 Generic Timer registers. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information about these registers.

Table 10.3. AArch32 Generic Timer registers
Name CRn Op1 CRm Op2 Reset Width Description
CNTFRQ c14 0 c0 0 UNK 32-bit

Counter-timer Frequency register

CNTPCT - 0 c14 - UNK 64-bit Counter-timer Physical Count register
CNTKCTL c14 0 c1 0 -[a] 32-bit Counter-timer Kernel Control register
CNTP_TVAL     c2 0 UNK 32-bit Counter-timer Physical Timer TimerValue register
CNTP_CTL       1



Counter-timer Physical Timer Control register

CNTV_TVAL     c3 0 UNK 32-bit

Counter-timer Virtual Timer TimerValue register

CNTV_CTL       1 [b] 32-bit

Counter-timer Virtual Timer Control register

CNTVCT - 1 c14 - UNK 64-bit

Counter-timer Virtual Count register

CNTP_CVAL   2     UNK 64-bit Counter-timer Physical Timer CompareValue register
CNTV_CVAL   3     UNK 64-bit Counter-timer Virtual Timer CompareValue register
CNTVOFF   4     UNK 64-bit

Counter-timer Virtual Offset register

CNTHCTL c14 4 c1 0


32-bit Counter-timer Hyp Control register
CNTHP_TVAL     c2 0 UNK 32-bit

Counter-timer Hyp Physical Timer TimerValue register

CNTHP_CTL       1 [b] 32-bit Counter-timer Hyp Physical Timer Control register
CNTHP_CVAL - 6 c14 - UNK 64-bit

Counter-timer Hyp Physical CompareValue register

[a] The reset value for bits[9:8, 2:0] is 0b00000.

[b] The reset value for bit[0] is 0.

[c] The reset value for bit[2] is 0 and for bits[1:0] is 0b11.

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