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Data cache tag and data encoding

The Cortex-A53 processor data cache consists of a 4-way set-associative structure. The number of sets in each way depends on the configured size of the cache. The encoding, set in Rd in the appropriate MCR instruction, used to locate the required cache data entry for tag and data memory is shown in Table 6.6. It is very similar for both the tag and data RAM access. Data RAM access includes an additional field to locate the appropriate doubleword in the cache line. The set-index range parameter (S) is determined by:

S = log2(Data cache size in bytes/4).

Table 6.6. Data cache tag and data location encoding
Bit-field of Rd Description
[31:30] Cache way
[29:S] Unused
[S-1:6] Set index
[5:3] Cache doubleword data offset, Data Register only
[2:0] Unused, RAZ

Data cache reads return 64 bits of data in Data Register 0 and Data Register 1. The tag information, MOESI coherency state, outer attributes, and valid, for the selected cache line is returned using Data Register 0 and Data Register 1 using the format shown in Table 6.7. The Cortex-A53 processor encodes the 4-bit MOESI coherency state across two fields of Data Register 0 and Data Register 1.

Table 6.7. Data cache tag data format
Register Bit-field Description
Data Register 1 [31] Parity bit if ECC is implemented, otherwise res0.
Data Register 1 [30:29] Partial MOESI State, from tag RAM. See Table 6.8.
Data Register 1 [28] Non-secure state (NS).
Data Register 1 [27:0] Tag Address [39:12].
Data Register 0 [31] Tag Address [11].
Data Register 0 [30:6] Reserved, res0.
Data Register 0 [5] Parity bit if ECC is implemented, otherwise res0.
Data Register 0 [4] Dirty copy bit if ECC is implemented, otherwise res0.
Data Register 0 [3] Outer Allocation Hint.
Data Register 0 [2] Outer Shareability, from Dirty RAM.
Data Register 0 [1:0] Partial MOESI state, from Dirty RAM. See Table 6.8.

The CP15 Data Cache Data Read Operation returns two entries from the cache in Data Register 0 and Data Register 1 corresponding to the 16-bit aligned offset in the cache line:

Data Register 0

Bits[31:0] data from cache offset+ 0b000.

Data Register 1

Bits[31:0] data from cache offset+ 0b100.

The 64 bits of cache data is returned in Data register 0 and Data register 1.

Table Table 6.8 describes the MOESI state.

Table 6.8. MOESI state
Tag RAM partial MOESI bits Dirty RAM partial MOESI bits MOESI state
00 xx Invalid (I)
01 x0 SharedClean (S)
x1 SharedDirty (O)
1x x0 UniqueClean (E)
x1 UniqueDirty (M)

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