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Program flow prediction

The following sections describe program flow prediction:

Predicted and non-predicted instructions

This section shows the instructions that the processor predicts. Unless otherwise specified, the list applies to A64, A32 and T32 instructions. As a general rule, the flow prediction hardware predicts all branch instructions regardless of the addressing mode, including:

  • Conditional branches.

  • Unconditional branches.

  • Indirect branches associated with procedure call and return instructions.

  • Branches that switch between A32 and T32 states.

However, some branch instructions are not predicted:

  • Data-processing instructions using the PC as a destination register.

  • The BXJ instruction.

  • Exception return instructions.

T32 state conditional branches

A T32 instruction set branch that is normally encoded as unconditional can be made conditional by inclusion in an If-Then (IT) block. Then it is treated as a conditional branch.

Return stack predictions

The return stack stores the address and, in AArch32, the A32 or T32 instruction set of the instruction after a procedure call type branch instruction. This address is equal to the link register value stored in r14 in AArch32 state or X30 in AArch64 state. The following instructions cause a return stack push if predicted:

  • BL.

  • BLX (immediate) in AArch32 state.

  • BLX (register) in AArch32 state.

  • BLR in AArch64 state.

In AArch32 state, the following instructions cause a return stack pop if predicted:

  • BX

  • LDR pc, [r13], #imm

  • LDM r13, {…pc}

  • LDM r13, {…pc}!

In AArch64 state, the RET instruction causes a return stack pop.

Because return-from-exception instructions can change processor privilege mode and security state, they are not predicted. This includes:

  • LDM (exception return)

  • RFE

  • SUBS pc, lr

  • ERET

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