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ACE transfers

The Cortex-A53 processor does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line starting with the critical word first. A burst does not cross a cache line boundary.

The cache linefill fetch length is always 64 bytes.

The Cortex-A53 processor generates only a subset of all possible AXI transactions on the master interface.

For WriteBack transfers the supported transfers are:

  • WRAP 4 128-bit for read transfers (linefills).

  • INCR 4 128-bit for write transfers (evictions).

  • INCR N (N:1, 2, or 4) 128-bit write transfers (read allocate).

For Non-cacheable transactions:

  • INCR N (N:1, 2, or 4) 128-bit for write transfers.

  • INCR N (N:1, 2, or 4) 128-bit for read transfers.

  • INCR 1 32-bit, 64-bit, and 128-bit for read transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for write transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive write transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive read transfers.

For Device transactions:

  • INCR N (N:1, 2, or 4) 128-bit read transfers.

  • INCR N (N:1, 2, or 4) 128-bit write transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit read transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit write transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive read transfers.

  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive write transfers.

For translation table walk transactions INCR 1 32-bit, and 64-bit read transfers.

The following points apply to AXI transactions:

  • WRAP bursts are only 128-bit.

  • INCR 1 can be any size for read or write.

  • INCR burst, more than one transfer, are only 128-bit.

  • No transaction is marked as FIXED.

  • Write transfers with none, some, or all byte strobes LOW can occur.

Table 7.8 shows the ACE transactions that can be generated, and some typical operations that might cause the transactions to be generated. This is not an exhaustive list of ways to generate each type of transaction, because there are many possibilities.

Table 7.8. ACE transactions
Transaction Operation
ReadNoSnoop Non-cacheable loads or instruction fetches. Linefills of non-shareable cache lines into L1 or L2.
ReadOnce Cacheable loads that are not allocating into the cache, or cacheable instruction fetches when there is no L2 cache.
ReadClean Not used.
ReadNotSharedDirty Not used.
ReadShared L1 Data linefills started by a load instruction, or L2 linefills started by an instruction fetch.
ReadUnique L1 Data linefills started by a store instruction.
CleanUnique Store instructions that hit in the cache but the line is not in a unique coherence state. Store instructions that are not allocating into the L1 or L2 caches, for example when streaming writes.
MakeUnique Store instructions of a full cache line of data, that miss in the caches, and are allocating into the L2 cache.
CleanShared Cache maintenance instructions.
CleanInvalid Cache maintenance instructions.
MakeInvalid Cache maintenance instructions.
DVM TLB and instruction cache maintenance instructions.
DVM complete DVM sync snoops received from the interconnect.
Barriers DMB and DSB instructions. DVM sync snoops received from the interconnect.
WriteNoSnoop Non-cacheable store instructions. Evictions of non-shareable cache lines from L1 and L2.
WriteUnique Not used.
WriteLineUnique Not used.
WriteBack Evictions of dirty lines from the L1 or L2 cache, or streaming writes that are not allocating into the cache.
WriteClean Evictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache maintenance instructions.
WriteEvict Evictions of unique clean lines, when configured in the L2ACTLR.
Evict Evictions of clean lines, when configured in the L2ACTLR.

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