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Memory interface attributes

Table 7.5 shows the ACE master interface attributes for the Cortex-A53 processor. The table lists the maximum possible values for the read and write issuing capabilities if the processor includes four cores.

Table 7.5. ACE master interface attributes
Attribute Value[a] Comments

Write issuing

capability

17 + n

The cluster can issue a maximum of 16 writes, excluding barriers:

  • Up to 16 writes to Normal memory that is both inner and outer write-back cacheable.

  • Up to 15 writes to all other memory types, including Device, Normal non-cacheable and Write-through.

Any mix of memory types is possible, and each write can be a single write or a write burst.

Each core can also issue a barrier and the cluster can issue an additional barrier.

Read issuing

capability

8n + 4m + 1

8 for each core in the cluster including up to:

  • 8 data linefills.

  • 4 non-cacheable or Device data reads.

  • 1 non-cacheable TLB page-walk read.

  • 3 instruction linefills.

  • 5 coherency operations.

  • 1 barrier operation.

  • 8 DVM messages.

    Note

    The 8 DVM messages per core can each be two part DVM messages, resulting in up to 16 DVM transactions per core.

If an ACP is configured, up to 4 ACP linefill requests can be generated. 1 barrier operation can be generated from the cluster.

Exclusive thread

capability

n Each core can have 1 exclusive access sequence in progress.

Write ID

capability

17 + n

The maximum number of outstanding write IDs is 21. This is the same as the maximum number of outstanding writes.

Only Device memory types with nGnRnE or nGnRE can have more than one outstanding transaction with the same AXI ID. All other memory types use a unique AXI ID for every outstanding transaction.

Write ID width 5 The ID encodes the source of the memory transaction. See Table 7.6.

Read ID

capability

8n + 4m + 1

8 for each core in the cluster in addition to:

  • 4 for the ACP.

  • 1 for barriers.

Only Device memory types with nGnRnE or nGnRE can have more than one outstanding transaction with the same AXI ID. All other memory types use a unique AXI ID for every outstanding transaction.

Two part DVMs use the same ID for both parts, and therefore can have two outstanding transactions on the same ID.

Read ID width 6 The ID encodes the source of the memory transaction. See Table 7.7.

[a] n is the number of cores.

m is 1 if the processor is configured with an ACP interface, and 0 otherwise.


Table 7.6 shows the encodings for AWIDM[4:0]

Table 7.6. Encodings for AWIDM[4:0]
Attribute Value Issuing capability per ID Comments
Write ID 0b000nn[a] 1 Core nn system domain store exclusive
0b001nn[a] 1 Core nn barrier
0b01000 0 Unused
0b01001 1 SCU generated barrier
0b0101x 0 Unused
0b011nn[a] 15 Core nn non-re-orderable device write
0b1xxxx 1 Write to normal memory, or re-orderable device memory

[a] Where nn is the core number 0b00, 0b01, 0b10, or 0b11.


Table 7.7 shows the Encodings for ARIDM[5:0]

Table 7.7. Encodings for ARIDM[5:0]
Attribute Value Issuing capability per ID Comments
Read ID 0b0000nn[a] 4 Core nn exclusive read or non-reorderable device read
0b0001nn[a] 1 Core nn barrier
0b001000 0 Unused
0b001001 1 SCU generated barrier or DVM complete
0b00101x 0 Unused
0b0011xx 0 Unused
0b01xx00 1 ACP read
0b01xx01 0 Unused
0b01xx1x 0 Unused
0b1xxxnn[a] 1 Core nn read

[a] Where nn is the core number 0b00, 0b01, 0b10, or 0b11.


Note

These ID and transaction details are provided for information only. ARM strongly recommends that all interconnects and peripherals are designed to support any type and number of transactions on any ID, to ensure compatibility with future products.

See the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite for more information about the ACE and AXI signals described in this manual.

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