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Memory interface attributes

Table 7.11 shows the CHI master interface attributes for the Cortex-A53 processor. The table lists the maximum possible values for the read and write issuing capabilities if the processor includes four cores.

Table 7.11. CHI master interface attributes
Attribute Value[a] Comments

Write issuing capability

Configuration dependent

The maximum number of writes varies, depending on the configuration of the processor:

  • The number of cores.

  • The presence of the L2 cache.

If no L2 cache is configured:

One core

5 outstanding writes.

2-4 cores

8 outstanding writes.

If an L2 cache is configured:

One core

7 outstanding writes.

2-4 cores

10 outstanding write.

A Cortex-A53 processor configured with four cores, with L2 cache, can issue 10 outstanding transactions. A Cortex-A53 processor configured with one core, without L2 cache, can issue five outstanding transactions.

All outstanding transactions use a unique ID.

Read issuing capability

8n + 4m + 1

8 for each core in the cluster including up to:

  • 8 data linefills.

  • 4 Non-cacheable or Device data reads.

  • 1 Non-cacheable TLB page-walk read.

  • 3 instruction linefills.

  • 5 coherency operations.

  • 1 barrier operation.

  • 8 DVM messages.

If an ACP is configured, up to 4 ACP linefill requests can be generated. 1 barrier operation is generated from the cluster.

Exclusive thread capability

n Each core can have 1 exclusive access sequence in progress.

Transaction ID width

8 The ID encodes the source of the memory transaction. See Table 7.6 and Table 7.7.

Transaction ID capability

8n + 4m + w + 1

8 for each core in the cluster in addition to:

  • 4 for the ACP interface.

  • 1 for barriers.

  • 6 to 11 writes, depending on the write issuing capability.

Unlike an AMBA 4 ACE configured Cortex-A53 processor, there is never any ID reuse, regardless of the memory type.

[a] n is the number of cores.

m is the ACP interface.

w is the write issuing capability plus one.

In a CHI configured Cortex-A53 processor, there is no fixed mapping between CHI transaction IDs and cores. Some transaction IDs can be used for either reads or writes.

See the ARM® AMBA® 5 CHI Protocol Specification for more information about the CHI signals described in this manual.

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