The optional integrated L2 configurable caches sizes are 128KB, 256KB, 512KB, 1MB, and 2MB.
Data is allocated to the L2 cache only when evicted from the L1 memory system, not when first fetched from the system. The only exceptions to this rule are for memory marked with the inner transient hint, or for non-temporal loads, see Non-temporal loads, that are only ever allocated to the L2 cache. The L1 cache can prefetch data from the system, without data being evicted from the L2 cache.
Instructions are allocated to the L2 cache when fetched from the system and can be invalidated during maintenance operations.
The L2 cache is 16-way set associative. The L2 cache tags are looked up in parallel with the SCU duplicate tags. If both the L2 tag and SCU duplicate tag hit, a read accesses the L2 cache in preference to snooping one of the other cores.
L2 RAMs are invalidated automatically at reset unless the L2RSTDISABLE signal is set HIGH when the nL2RESET signal is deasserted.