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Performance Monitors Common Event Identification Register 1

The PMCEID1_EL0 characteristics are:

Purpose

Defines which common architectural and common microarchitectural feature events are implemented.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

Config RO RO RO RO RO

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.

Configurations

The PMCEID1_EL0 is architecturally mapped to:

Attributes

PMCEID1_EL0 is a 32-bit register.

Figure 12.4 shows the PMCEID1_EL0 bit assignments.

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Table 12.7 shows the PMCEID1_EL0 bit assignments.

Table 12.7. PMCEID1 bit assignments
Bits Name Function
[31:1] -  
[32] CE[32]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in Table 12.8, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.


Table 12.8. PMU common events
Bit Event number Event mnemonic Description
[0] 0x20 L2D_CACHE_ALLOCATE
0

This event is not implemented.


To access the PMCEID1_EL0:

	
MRS <Xt>, PMCEID1_EL0; Read Performance Monitor Common Event Identification Register 0

The PMCEID1_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE24.

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