Component Identification Registers
There are four read-only Component Identification Registers, Component ID0 through Component ID3. Table 12.23 shows these registers.
Register | Value | Offset |
---|---|---|
Component ID0 | 0x0D |
0xFF0 |
Component ID1 | 0x90 |
0xFF4 |
Component ID2 | 0x05 |
0xFF8 |
Component ID3 | 0xB1 |
0xFFC |
The Component Identification Registers identify Performance Monitor as ARM PMUv3 architecture. The Component ID registers are:
Component Identification Register 0
The PMCIDR0 characteristics are:
- Purpose
-
Provides information to identify a Performance Monitor component.
- Usage constraints
-
The PMCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR0 by condition code is:
Off DLK OSLK EPMAD SLK Default - - - - RO RO Table 12.1 describes the condition codes.
- Configurations
-
The PMCIDR0 is in the Debug power domain.
- Attributes
-
See the register summary in Table 12.15.
Figure 12.14 shows the PMCIDR0 bit assignments.
Table 12.24 shows the PMCIDR0 bit assignments.
Bits | Name | Function |
---|---|---|
[31:8] | - |
Reserved, res0. |
[7:0] | Size |
|
The PMCIDR0 can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0xFF0
.
Component Identification Register 1
The PMCIDR1 characteristics are:
- Purpose
-
Provides information to identify a Performance Monitor component.
- Usage constraints
-
The PMCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR1 by condition code is:
Off DLK OSLK EPMAD SLK Default - - - - RO RO Table 12.1 describes the condition codes.
- Configurations
-
The PMCIDR1 is in the Debug power domain.
- Attributes
-
See the register summary in Table 12.15.
Figure 12.15 shows the PMCIDR1 bit assignments.
Table 12.25 shows the PMCIDR1 bit assignments.
Bits | Name | Function |
---|---|---|
[31:8] | - |
Reserved, res0. |
[7:4] | CLASS |
|
[3:0] | PRMBL_1 |
|
The PMCIDR1 can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0xFF4
.
Component Identification Register 2
The PMCIDR2 characteristics are:
- Purpose
-
Provides information to identify a Performance Monitor component.
- Usage constraints
-
The PMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default - - - - RO RO Table 12.1 describes the condition codes.
- Configurations
-
The PMCIDR2 is in the Debug power domain.
- Attributes
-
See the register summary in Table 12.15.
Figure 12.16 shows the PMCIDR2 bit assignments.
Table 12.26 shows the PMCIDR2 bit assignments.
Bits | Name | Function |
---|---|---|
[31:8] | - |
Reserved, res0. |
[7:0] | PRMBL_2 |
|
The PMCIDR2 can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0xFF8
.
Component Identification Register 3
The PMCIDR3 characteristics are:
- Purpose
-
Provides information to identify a Performance Monitor component.
- Usage constraints
-
The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR3 by condition code is:
Off DLK OSLK EPMAD SLK Default - - - - RO RO Table 12.1 describes the condition codes.
- Configurations
-
The PMCIDR3 is in the Debug power domain.
- Attributes
-
See the register summary in Table 12.15.
Figure 12.17 shows the PMCIDR3 bit assignments.
Table 12.27 shows the PMCIDR3 bit assignments.
Bits | Name | Function |
---|---|---|
[31:8] | - |
Reserved, res0. |
[7:0] | PRMBL_3 |
|
The PMCIDR3 can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0xFFC
.