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Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv3 architecture. There is a set of eight registers, listed in register number order in Table 12.17.

Table 12.17. Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4 0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0xD3 0xFE0
Peripheral ID1 0xB9 0xFE4
Peripheral ID2 0x4B 0xFE8
Peripheral ID3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The Peripheral ID registers are:

Peripheral Identification Register 0

The PMPIDR0 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

Usage constraints

The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR0 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 12.1 describes the condition codes.

Configurations

The PMPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 12.15.

Figure 12.9 shows the PMPIDR0 bit assignments.

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Table 12.18 shows the PMPIDR0 bit assignments.

Table 12.18. PMPIDR0 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:0] Part_0
0xD3

Least significant byte of the performance monitor part number.


The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

Peripheral Identification Register 1

The PMPIDR1 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

Usage constraints

The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR1 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 12.1 describes the condition codes.

Configurations

The PMPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 12.15.

Figure 12.10 shows the PMPIDR1 bit assignments.

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Table 12.19 shows the PMPIDR1 bit assignments.

Table 12.19. PMPIDR1 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0] Part_1
0x9

Most significant nibble of the performance monitor part number.


The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Peripheral Identification Register 2

The PMPIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

Usage constraints

The accessibility to the PMPIDR2 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 12.1 describes the condition codes.

The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.

Configurations

The PMPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 12.15.

Figure 12.11 shows the PMPIDR2 bit assignments.

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Table 12.20 shows the PMPIDR2 bit assignments.

Table 12.20. PMPIDR2 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Revision
0x4

r0p4.

[3] JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0] DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Peripheral Identification Register 3

The PMPIDR3 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

Usage constraints

The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR3 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 12.1 describes the condition codes.

Configurations

The PMPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 12.15.

Figure 12.12 shows the PMPIDR3 bit assignments.

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Table 12.21 shows the PMPIDR3 bit assignments.

Table 12.21. PMPIDR3 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] REVAND
0x0

Part minor revision.

[3:0] CMOD
0x0

Customer modified.


The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Peripheral Identification Register 4

The PMPIDR4 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

Usage constraints

The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR4 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

Table 12.1 describes the condition codes.

Configurations

The PMPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 12.15.

Figure 12.13 shows the PMPIDR4 bit assignments.

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Table 12.22 shows the PMPIDR4 bit assignments.

Table 12.22. PMPIDR4 bit assignments
Bits Name Function
[31:8] -

Reserved, res0.

[7:4] Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.

[3:0] DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They are reserved for future use and are res0.

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