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AArch32 execution modes

ARMv7 and earlier versions of the ARM architecture define a set of named processor modes, including modes that correspond to different exception types. For compatibility, AArch32 state retains these processor modes.

Table 3.3 shows the AArch32 processor modes, and the exception level of each mode.

Table 3.3. AArch32 processor modes and associated exception levels
AArch32 processor mode EL3 using Security state Exception level
User AArch32 or AArch64 Non-secure or Secure EL0
System, FIQ, IRQ, Supervisor, AArch64 Non-secure or Secure EL1
Abort, Undefined AArch32 Non-secure EL1
    Secure EL3
Hyp AArch32 or AArch64 Non-secure only EL2
Monitor AArch32 Secure only EL3

When the EL3 using column of Table 3.3 shows:


The row refers to information shown in Figure 3.1.


The row refers to information shown in Figure 3.2.

A processor mode name does not indicate the current security state. To distinguish between a mode in Secure state and the equivalent mode in Non-secure state, the mode name is qualified as Secure or Non-secure. For example, a description of AArch32 operation in EL1 might reference the Secure FIQ mode, or to the Non-secure FIQ mode.

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